摘要
针对自适应接收机中高速A/D采样数据对高带宽和大容量的需求,提出一种DDR3控制器设计方案。采用在MIG IP核的基础上添加用户接口控制程序的设计方法,利用ZC706评估板实现了DDR3的读写控制。设计方案具有较高的可移植性和简单的用户接口,可以灵活地应用到不同的工程中。仿真和板级测试表明,DDR3可在800 MHz的接口频率工作,传输速度可达1 600 MT/s,验证了系统的可行性和正确性,其将有助于解决海量数据的高速缓存问题。
Aiming at the requirements of high bandwidth and large capacity for high - speed A/D sampling data in adaptive receiver, a designscheme of double data rate 3 （ DDR3） controller is put forward. The design method of adding a user interface control program based on MIG IPcore is adopted, and the controller is realized using ZC706 evaluation board. The design has better flexibility, high transplantability, and simpleuser interface,which can be flexibly applied into different projects. Through the simulation and board level test,the interfacing frequency ofDDR3 can work at 800 MHz,and the transmission speed is up to 1 600 MT/s,which verifies the feasibility and correctness of the system,andwill have a significant impact to solve the problem of massive data cache.
出处
《自动化仪表》
CAS
2016年第8期5-7,12,共4页
Process Automation Instrumentation
基金
国防基础科研计划基金资助项目(编号:B3120133002)
关键词
存储器
控制器
FPGA
高带宽
大容量
用户接口
数据模块
模数转换
Memory Controller FPGA High bandwidth Large capacity User interface Data module Analog - digital conversion
