摘要
提出一种能够工作在低电压下的SRAM存储单元,单元采用8T结构,在传统6T结构的基础上增加两个串联的NMOS构成读出端口,传统6T结构中背靠背反相器采用高阈值晶体管.采用Smic130nm工艺仿真结果显示,提出的8T结构能够在最低0.3V下正常操作,单元的读写噪声容限,保持噪声容限,相比传统6管结构显著提升,并且低电压下静态功耗方面均比传统6管结构降低60%~70%.
This paper presents a novel SRAM bitcell structure which is applied for ultra-low voltage. The biteell is composed of 8 transistors, two additional NMOS transistors in series is added to traditional 6T structure as a read out port. Besides, the back to back to inverter is designed by high threshold voltage transistors. Simulations in simic 130 nm process are operated. The simulation results show that the hold and read static noise margin of proposed bitcell have enhanced greatly comparing to conventional 6T, additionally, this new biteell can operate correctly in ultra-low voltage region. Comparing to conventional 6T cell, the static power consuming of this bitcell is reduced by 60%~70% in low voltage region.
出处
《微电子学与计算机》
CSCD
北大核心
2016年第9期15-18,23,共5页
Microelectronics & Computer
基金
中国科学院战略性先导科技专项极低功耗智能感知技术(XDA06020401)
