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面向数据Cache的片上存储动态优化

On-Chip Storage Dynamic Optimization Oriented Data-Cache
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摘要 提出一种数据Cache片上可重构存储系统,将程序不同阶段利用率低的数据Cache配置为SPM(scratch-pad memory),将访问频繁/冲突严重的数据页映射到SPM,动态降低能耗。在数据Cache要求提高时,再将SPM配置为Cache,提高Cache命中率。利用程序基本块向量法监测、区分程序不同阶段,建立数据Cache数学模型,基于程序运行阶段和时间域分割的Cache相变图统计数据页使用情况,决定放入SPM的数据页。仿真实验结果显示,采用所提出的片上可重构存储系统后,8KB4、16KB4和32KB4路关联Cache,平均能耗分别降低10.15%、11.35%和12.45%,系统性能明显提升。 An on-chip re-configurable storage system is introduced for data-Cache.According to the different program stages,Cache with low utilization rate is configured as SPM(scratch-pad memory),and those data pages which are frequently accessed or cause serious Cache conflict,will be mapped to SPM,thus the system energy is reduced dynamically.While program needs high Cache performance,these memories will be configured back to Cache,which will improve Cache hit-rate.A program is divided into different stages based on basicblock-vector method,and a mathematical model is established for data-Cache.A Cache phase-change diagram which is based on program stages and time dimension slice,is used to count and analyze the utilization of data pages,and decides which data pages to be remapped to SPM.The experimental results indicate that after the on-chip re-configurable storage is implemented,Cache is associated with 8KB4,16KB4 and 32KB4,the average energy consumption of the storage system is reduced by 10.15%,11.35%and 12.45%respectively,the system performance is improved obviously.
作者 徐涛
出处 《测控技术》 CSCD 2016年第11期70-76,共7页 Measurement & Control Technology
关键词 数据高速缓存 便笺式存储器 可重构存储 低功耗 Cache SPM re-configurable storage low energy
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