期刊文献+

应用设计过程的胚胎硬件细胞单元粒度优化方法 被引量:7

Cell granularity optimization method of embryonics hardware in application design process
原文传递
导出
摘要 胚胎硬件的高可靠性主要由新颖的硬件体系和细胞电路结构来保障,缺乏应用设计过程的可靠性提高方法研究。分析了在应用设计过程中可调的胚胎硬件可靠性影响因素,针对细胞单元粒度不同会导致细胞面积变化从而影响细胞阵列可靠性的实际情况,对传统可靠性模型无法体现细胞面积变化的不足进行了改进,建立了新的可靠性模型。通过实例分析,总结出不同细胞单元粒度情况下的细胞阵列可靠性变化规律,进而给出细胞单元粒度优化选择方法,设计者基于该方法不需设计完整电路就能确定自身设计能力范围内获得最大可靠性的细胞单元粒度。 The high reliability of embryonJcs hardware is supported by the novel architecture of reconfigurable cellular array. During the application design process, research on the method to improve the reliability is scarce. In this paper, those fac- tors adjustable by designer in the application process have been extracted out, which affect the reliability of embryonics hardware. In embryonic hardware, cell area will change in different cell granularity, which is followed by the change of cel- lular array reliability. To solve this problem, a new reliability model is proposed for the traditional reliability model does not have parameters to express the area change of cells. After the reliability analysis of examples, variation laws of cellular array reliability with different cell granularity are summarized, and a cell granularity optimization method is raised. Based on the method, designers can Choose the optimal cell granularity without a complete design of cellular array.
作者 张砦 王友仁
出处 《航空学报》 EI CAS CSCD 北大核心 2016年第11期3502-3511,共10页 Acta Aeronautica et Astronautica Sinica
基金 国家自然科学基金(61202001 61402226)~~
关键词 胚胎硬件 可靠性分析 电路优化 细胞单元粒度 可重构 embryonics hardware reliability analysis circuit optimization cellular granularity reconflgurable
  • 相关文献

参考文献5

二级参考文献50

  • 1高娜娜,李占才,王沁.一种可重构体系结构用于高速实现DES、3DES和AES[J].电子学报,2006,34(8):1386-1390. 被引量:19
  • 2林勇,罗文坚,钱海,王煦法.n×n阵列胚胎电子系统应用中的优化设计问题分析[J].中国科学技术大学学报,2007,37(2):171-176. 被引量:9
  • 3任小西,李仁发,金声震,张克环,吴强.基于JBits的一种可重构数据处理系统可靠性研究[J].计算机研究与发展,2007,44(4):722-728. 被引量:3
  • 4伏见正则著 李明哲译.概率论和随机过程[M].北京:世界图书出版公司,1997..
  • 5Cheatham J A, Emmert J M, Baumqart S, A survey of fault tolerant methodologies for FPGAs[J]. ACM Transactions on Design Automation of Electronic Systems, 2006, 11(2): 501-533.
  • 6Doumar A, Katoh K, lto H. Fault tolerant SoC architecture design for JPEG2000 using partial reconfigurability[C]//Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems4. Piscataway, NJ, USA: IEEE, 2007: 30-40.
  • 7Emmert J M, Stroud C E, Abramovici M. Online fault tolerance for FPGA logic blocks[J]. IEEE Transactions on Very Large Scale Integration (VISI) Systems, 2007, 15(2): 216-226.
  • 8Zhang Z, Wang Y R, Yang S S, et al. The research of selfrepairing digital circuit based on embryonic cellular array[J]. Neural Computing & Applications, 2008, 17(2): 145-151.
  • 9Canham R O, Tyrrell A M. A hardware artificial immune system and embryonic array for fault tolerant systems[J]. Genetic Programming and Evolvable Machines, 2003, 4(4): 359-382.
  • 10Barker W, Halliday D M, Thoma Y, et al. Fault tolerance using dynamic reconfiguration on the POEtic tissue[J]. IEEE Transactions on Evolutionary Computation, 2007, 11 (5): 666-684.

共引文献40

同被引文献44

引证文献7

二级引证文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部