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基于多相位插值的视频缩放系统FPGA实现 被引量:2

Implementation of video scaling system using FPGA based on poly-phase interpolation algorithm
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摘要 传统的插值算法在视频图像缩放尤其是输出高分辨率的视频图像时,对细节方面的处理性能较差。采用多相位插值算法实现视频图像缩放,主要阐述算法的原理及算法实现的硬件结构。其中硬件电路控制部分使用Xilinx公司的Spartan6系列FPGA芯片,系统可以实现将四路摄像头采集的视频信号从任意通道放大到1 920x1 080@60 Hz的分辨率显示,结果表明输出视频图像的实时性和细节保持良好。 Traditional interpolation algorithm has a lower quality on processing video image scaling details, especially when outputing higher spatial resolution video image. This paper mainly describes the algorithm principle and the hardware architecture of video image scaling using the poly-phase interpolation algorithm. Its hardware is implemented by using Xilinx' s Spartan6 series FPGA chip. The system can enlarge a video signal captured by four cameras to 1 920×1080@ 60 Hz resolution on any channel. The results show that hardware system can output vide- o images in real time and keep good details.
出处 《微型机与应用》 2016年第24期46-49,共4页 Microcomputer & Its Applications
关键词 视频缩放 多相位 FPGA 实时性 video scaling poly-phase FPGA real-time
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