摘要
针对ARM并行阵列机结构,提出了与之相适应的通信结构,采用4个路由器完成16个处理器内核之间的通信,有效地节约了面积.该路由器采用基于数据包交换的片上网络通信方式,内部运用缓存机制、经典的XY路由算法和专用的仲裁策略再加入数据多播,且处理器选用低功耗、高性能的ARM内核,通过采用以上机制能够有效降低数据传播延迟和功耗.实验结果表明采用该方案设计的路由器时钟频率最高可达406.009 MHz,能够满足该ARM阵列机对于通信速率的要求.
Routing communication structure designed in this paper＇s project involves calls ARM parallel array processors that use four routers to complete the communication between the 16-core processors. Therefore it makes the area reduced at a greater degree. The router uses the way of Noc （Network on Chip） communication that is based on the packet switching , it uses internal caching mechanism, classic XY router algorithms, dedicated arbitration policy and data multicast, and with low power of high-performance ARM processor, these mechanisms reduce the data propagation delay and power consumption at the same time. Makes the performance of communication between multi-core processors has been increased greatly. The result shows that the clock frequency of the router, which designs for the telecommunications in the array of ARM muti-core machine, is up to 406. 009MHz and the router can better meet the performance requirements of the array of ARM muff-core machine.
出处
《微电子学与计算机》
CSCD
北大核心
2017年第2期73-76,82,共5页
Microelectronics & Computer
关键词
路由器
缓存机制
经典XY路由算法
核间通信
数据多播
router
caching mechanism
classic XY router algorithms
communication between multi-core processors
data multicast
