摘要
针对维特比译码器译码过程中速度制约的问题,设计了一种结构优化的维特比译码器。该结构通过蝶形单元的直通互连,使得在状态转移过程中不需要对路径度量值进行大范围存储,简化了路径度量值的存储与读取逻辑。并且可以根据不同的应用要求灵活配置蝶形处理单元的复用次数。最后,结合FPGA平台,利用Verilog硬件描述语言和Vivado软件对译码器进行设计与实现。综合实现结果表明,该译码器占用1 564个LUT单元,能够在100 MHz系统时钟下进行有效译码。
In order to solve the problem of speed control in the decoding process of Viterbi decoder,a structure optimized Viterbi decoder is designed. Through the direct interconnection of the butterfly units,it is not necessary to store the path metric value during the state transition process,and the storage and reading logic of the path metric value is simplified. And the reuse times of butterfly processing units can be configured flexibly,according to different application requirements. Finally,combined with the FPGA platform,using Verilog hardware description language and Vivado software to design and implement the decoder. Implementation results show that the decoder occupies 1 564 LUTs of the FPGA,and can decode effectively under 100 MHz system clock.
作者
黄增先
王进华
Huang Zengxian Wang Jinhua(School of Electrical Engineering and Automation, Fuzhou University, Fuzhou 350108, China)
出处
《微型机与应用》
2017年第5期60-64,共5页
Microcomputer & Its Applications
关键词
维特比
回溯
蝶形单元
加比选
状态转移因子
FPGA
Viterbi
trace-back
butterfly unit
Add-Compare-Select（ACS）
state transfer factor
FPGA
