摘要
提出了一种基于硅通孔(TSV)和激光刻蚀辅助互连的改进型CMOS图像传感器(CIS)圆片级封装方法。对CIS芯片电极背部引出的关键工艺,如锥形TSV形成、TSV绝缘隔离、重布线(RDL)等进行了研究。采用低温电感耦合等离子体增强型化学气相淀积(ICPECVD)的方法实现TSV内绝缘隔离;采用激光刻蚀开口和RDL方法实现CIS电极的背部引出;通过采用铝电极电镀镍层的方法解决了激光刻蚀工艺中聚合物溢出影响互连的问题,提高了互连可靠性。对锥形TSV刻蚀参数进行了优化。最终在4英寸(1英寸=2.54 cm)硅/玻璃键合圆片上实现了含有276个电极的CIS圆片级封装。电性能测试结果表明,CIS圆片级封装具有良好的互连导电性,两个相邻电极间平均电阻值约为7.6Ω。
An improved wafer level packaging method of CMOS image sensor（ CIS） based on through-silicon via（ TSV） and laser etching assisted interconnection was proposed. Several key processes for the backside leading-out were studied,such as tapered TSV fabrication,TSV insulated isolation and redistribution layer（ RDL）,etc. The isolation layer inside TSV was formed by using low temperature inductively coupled plasma-enhanced chemical vapor deposition（ ICPECVD） method. Then the backside leading-out of the CIS electrode was realized by laser-etched opening method and RDL method. By using the method of electroplating nickel layer on aluminum electrode,the influence of polymer overflow on interconnection in laser etching process was effectively overcome. The interconnection reliability was improved. The etching parameters of the taper TSV were optimized. Finally,the CIS wafer-level package with 276 electrodes was successfully fabricated on the 4-inch（ 1 inch = 2. 54 cm） Si/glass bonding wafer.The electrical performance tests results show that the CIS wafer-level package has a good electrical interconnection with an average resistance of about 7. 6 Ω between two nearby electrodes.
出处
《半导体技术》
CSCD
北大核心
2017年第8期636-640,共5页
Semiconductor Technology
基金
国家自然科学基金资助项目(61574154)
上海市自然科学基金资助项目(13ZR1447300)
