期刊文献+

一种基于分层Mesh网络的层次化NoC拓扑结构 被引量:4

A Hierarchical NoC Topology Based on Layered Mesh Network
下载PDF
导出
摘要 针对片上网络中距离较远节点之间通信延迟过大的问题,提出一种层次化HDMesh拓扑结构。该拓扑结构采用分层设计,底层网络使用Mesh结构互连进行临近节点通信,顶层网络在Mesh结构的基础上增加2条对角链路以降低通信延迟。为避免顶层网络的拥塞,设计相应的HDXY路由算法,对各层流量进行合理分配。实验结果表明,在Rent流量模式下,相比Mesh,CMesh和CHMesh拓扑结构,HDMesh拓扑结构具有更低的通信延迟和更高的网络吞吐量。 Communication delay increases sharply with the expansion of distance between the nodes in the network on chip. In order to solve this problem,this paper proposes a Hierarchical Diagonal Mesh(HDMesh) topology. The topology adopts hierarchical design. The base-level is connected by Mesh for the communication between adjacent nodes. On the top level, two diagonal links are added in the Mesh architecture to further reduce the communication delay. To avoid the congestion on the top level network, a Hierarchical Diagonal XY (HDXY) routing algorithm is proposed to assign the flow rate of each layer reasonably. The experimental results show that,compared with Mesh,CMesh and CHMesh in the Rent flow mode,HDMesh has lower communication latency and higher network throughput.
出处 《计算机工程》 CAS CSCD 北大核心 2017年第10期1-5,共5页 Computer Engineering
基金 国家自然科学基金面上项目(61572520)
关键词 片上网络 层次化 拓扑结构 路由算法 Rent流量模式 Network on Chip ( NoC ) hierarchical topology routing algorithm Rent flow mode
  • 相关文献

参考文献3

二级参考文献31

  • 1朱晓静,胡伟武,马可,章隆兵.Xmesh:一个mesh-like片上网络拓扑结构[J].软件学报,2007,18(9):2194-2204. 被引量:17
  • 2MARCULESCU R, OGRAS U Y, SHIUAN P L, et al. Outstanding research problem in NoC design: system, microarchitecture, and circuit perspectives [ J]. IEEE Transactions on Computer-Aided De- sign of Integrated Circuit and System, 2009, 28(1) :3 -21.
  • 3CHIU G M. The odd-even turn model for adaptive routing [ J]. IEEE Transactions on Parallel and Distributed Systems, 2000, 11 (7) : 729 - 738.
  • 4KUO Y H, TSAI P A. Path-diversity-aware adaptive routing in net- work on chip systems [ C]// Proceedings of the 6th International Symposium on Embedded Muhicore SoCs. Washington, DC: IEEE Computer Society, 2012:175 - 182.
  • 5JERGER N E, PEH L S. On-chip networks [ M]. New York: Mor- gan and Claypool, 2009: 67- 78.
  • 6WANG J, GU H. Energy and buffer aware adaptive routing algo- rithm for network-on-chip [ J]. Microelectronics Journal, 2013, 44 (2) : 137 - 144.
  • 7ASCIA G, CATANIA V, PALESI M. Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip [ J]. IEEE Transactions on Computers, 2008, 57(6) : 809 - 920.
  • 8WINTER M, PRUSSEIT S, FETlnEIS G P. Hierarchical routing architectures in clustered 2D-mesh networks-on-chip [ C]// Pro- ceedings of International SoC Design Conference. Seoul: IEEE Cir-cuits and Systems Society Press, 2010:388 -391.
  • 9TANG M, WU C. A case study of the odd-even tum model [ C]//Proceedings of the 2nd International Conference on Consumer Elec- tronics, Communications and Networks. Piscataway: IEEE Press, 2012:3005 -3008.
  • 10FAZZINO F, PALESI M. Noxim: network-on-chip simulator [ EB/ OL]. [ 2013-10-12]. http://sourceforge, net/projects/noxim.

共引文献8

同被引文献33

引证文献4

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部