摘要
随着半导体的生产技术进入纳米级,大规模集成电路(VLSI)的集成度不断被提高。由于互连线之间的间距被迅速缩少,故互连线的耦合串扰效应已经严重影响了VLSI的整体性能。首先,提出一个三线耦合的等效电路模型,该模型结合了耦合电容和互感电感;其次,在该等效电路模型的基础上,通过运用解耦技术和ABCD参数矩阵的方法构造一个精确计算三线耦合的互连串扰延时模型;此外,还对比和分析了双线耦合和三线耦合的延时性能;最后,研究互连间距对串扰延时的影响。实验数据结果显示,采用非并行布线规则和增大互连间距均能有效降低串扰延时,提出的多根互连线的串扰延时模型和Spice仿真结果保持了高度的一致性。
With the semiconductor production technology going into the nanoscale level,the integration level of the very large scale integrated circuit（VLSI）is constantly improved. The coupling crosstalk effect of interconnected lines has seriously affected the overall performance of the VLSI due to the rapid reduction of the spacing between interconnected lines. Therefore,an equivalent circuit model based on three-line coupling is proposed,in which coupling capacitance and mutual inductance are combined. On the basis of the equivalent circuit model,an interconnection crosstalk delay model for accurate calculation of three-line coupling was constructed by adopting the decoupling technique and ABCD parameter matrix approach. The time delay performances of two-line coupling and three-line coupling were compared and analyzed. The influence of interconnection spacing on crosstalk delay was studied. The results from experimental data show that both applying the non-parallel routing rule and increasing the interconnection spacing can effectively reduce the crosstalk delay. The proposed crosstalk delay model for multiple interconnected lines maintains high consistency with the SPICE simulation results.
作者
续朋
潘中良
XU Peng;PAN Zhongliang(School of Physics and Telecommunications Engineering, South China Normal University, Guangzhou 510006, China)
出处
《现代电子技术》
北大核心
2018年第12期19-23,27,共6页
Modern Electronics Technique
基金
国家自然科学基金资助项目(61072028)
广东省科学计划基金资助项目(2016B090918071)
广州科学计划基金资助项目(201510010169)
广东省国家自然科学基金资助项目(2014A030313441)~~
