摘要
积分梳状(CIC)滤波器是一种高效的滤波器,广泛应用于无线通信技术的数字下变频和上变频端.但传统结构的级联CIC滤波器每个寄存器的位宽是固定的,在处理低频信号会造成高频的运算带宽过大,浪费计算机硬件资源的不足.利用Hogenauer"剪除"理论对每一级的输出位宽进行截短,提高CIC滤波器的性能,通过级联多个单级CIC滤波器优化其结构,构建了多级CIC滤波器;同时利用FPGA技术的重构性强、扩展性好、硬件资源占有少、成本低、可靠性高的特点,采用Verilog HDL语言设计实现了各个模块,最终基于FPGA设计完成的多级CIC滤波器模型,不仅节约了硬件资源,还使CIC滤波器每个寄存器的位宽可变.通过Modelsim对模型进行仿真并下载到以Altera DE2的EP2C35F672C6为目标芯片验证,达到了设计要求.
The integral comb （ CIC ） filter is an efficient filter which is widely used in the digital subfrequency conversion and frequency conversion of wireless communication technology. However, the level width of each register of the traditional structure is fixed, and the low frequency signal can cause high frequency operation band- width and waste the shortage of computer hardware resources.This paper, by using Hogenauer ＂cut off＂ theory on each level of output bits wide truncated, improve the performance of CIC filter, through a cascade of multiple single stage CIC filter to optimize its structure, building the multi-stage CIC filter.At the same time using FPGA technology is strong, good extensibility and occupies less hardware resources, the characteristics of low cost, high reliability, using Verilog HDL language design the various modules, the final model of multistage CIC filter based on FPGA design, not only save the hardware resources, but also make the CIC filter each register bits wide variable.The model was simulated by Modelsim and downloaded to the EP2C35F672C6 of Altera DE2 as the target chip verification, which met the design requirements.
作者
王璞
张玉明
田野
张坤
杨军
WANG Pu;ZHANG Yu-ming;TIAN Ye;ZHANG Kun;YANG Jun(School of Information Science and Engineering, Yunnan University, Kunming 650500, Chin)
出处
《云南大学学报（自然科学版）》
CAS
CSCD
北大核心
2018年第4期676-681,共6页
Journal of Yunnan University(Natural Sciences Edition)
基金
国家自然科学基金(11663007)
