摘要
为了最大限度地提高主机通过PCIe总线与外设之间的传输速度,设计了一种基于FPGA的异步传输系统。在内嵌PCIe IP核FPGA中设计了TLP引擎和SG-DMA控制器,前端与主机内存中的环形队列交互数据,后端使用FIFO缓存数据包,整个传输和处理过程的6个阶段可以异步并行工作。经过实验测试,在包长1 024字节的情况下,传输速度可达6.165Gbps;同时证实了异步工作模式的有效性,以及包长对传输速度的影响。文章所述的设计方案具有普遍的适应性,在数据加密卡、信号处理、TOE网卡等领域均可应用。
In order to maximize the transmission speed between host and peripheral by PCIe bus,an asynchronous system based on FPGA is designed.TLP transmission engine and SG-DMA controller are built inside FPGA embedded with a PCIe IP core.The front end interacts the data with the ring queue in host memory,the back end uses FIFO to cache the packets.The whole process can be divided into six phases which may work simultaneously and asynchronously.The experiment results show that the transmission speed is up to 6.165 Gbps when the testing packet is 1024 byte.The advantages of asynchronous mode is proved,relationship between transmission speed and packet length is disclosed.This design is universally adapted and can be applied to crypto card,digital signal process and TOE card.
作者
王元强
聂云杰
朱孟江
葛红舞
Wang Yuanqiang;Nie Yunjie;Zhu Mengjiang;Ge Hongwu(NARI Group Corporation（State Grid Electric Power Research Institute）,Nanjing 210003,China)
出处
《单片机与嵌入式系统应用》
2018年第8期62-64,68,共4页
Microcontrollers & Embedded Systems
