摘要
高性能数据转换器是第五代移动通信基站系统的核心器件,其采样速率不低于3 GS/s、分辨率高于12 bit,因此高速串行接口取代传统接口电路成为必然趋势。基于JESD204B协议设计了一种应用于3 GS/s 12 bit ADCs的高速串行接口控制层电路。在保证高速传输的前提下,折中考虑功耗和资源,该电路在传输层采用预分频技术完成组帧;在数据链路层采用极性信息简化编码技术实现8 B/10 B编码。在Vivado 16.1环境下,采用Xilinx公司的ZC706 FPGA中PHY IP和JESD204B Receiver IP完成控制层接口电路的验证。实验结果表明数据传输正确,且串化后的传输速度达到7.5 Gb/s,相较于同类型的接口设计,其传输速度提高了50%。
High performance data converter is the core device of the fifth generation mobile communication base station system. Its sampling rate is no less than 3 GS/s and the resolution is higher than 12 bit. Therefore, it is inevitable for high-speed serial inter-face to replace traditional interface circuits. Based on JESD204 B protocol, this paper designs a high speed serial interface control layer circuit applied to 3 GS/s 12 bit ADCs. Under the premise of ensuring high-speed transmission, it considers the power con-sumption and resources in the compromise. The circuit adopts the pre-frequency technique to complete the framing in the transmis-sion layer, and the 8 B/10 B coding is implemented by using the polar information to simplify encoding techniques in the data link layer. In Vivado 16. 1 environment, using the Xilinx ZC706 FPGA PHY IP and JESD204 B Receiver IP, the verification of the in-terface circuit proposed in this paper is completed. The experimental results show that the data transmission is correct, the serial-ized transmission speed is 7. 5 Gb/s. Compared with the same type interface design, the transmission speed is increased by 50 %.
作者
蒋林
衡茜
张春茗
邓军勇
王喜娟
Jiang Lin;Heng Qian;Zhang Chunming;Deng Junyong;Wang Xijuan(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China)
出处
《电子技术应用》
2018年第8期47-51,共5页
Application of Electronic Technique
基金
新一代宽带无线移动通信网科技重大专项(2016ZX03001003-006)
国家自然科学基金(61772417
61272120)
国家自然科学基金重点项目(61634004)
陕西省科技统筹创新工程项目(2016KTZDGY02-04-02)
