摘要
为了提高多周期CPU流水线的效率,在指令存储器和数据存储器的数据读取中设计发送地址在上升沿、读取数据在下降沿,从而实现译码和访存在一个周期内完成。在取指级不再单独设置加法器,把PC+4放在ALU中完成。通过大量的多路选择器与数据交互总线来进行数据联通。采用Verilog HDL语言设计出CPU,并在VIVADO平台上实现仿真,最后通过龙芯公司的LS-CPU-EXB-002试验箱来进行验证,结果表明所设计的多周期CPU的有效性。
In order to improve the efficiency of the multi-cycle CPU pipeline, the designation of the sending ad-dress is on the rising edge and the reading data is on the falling edge in the data reading of the instruction memory and the data memory, so that the decoding and the access are completed in one cycle. The adder is no longer set separately at the fetch level,and PC+4 is placed in the ALU. Data communication is performed through a large number of multiplexers and data exchange buses. The CPU was designed using Verilog HDL language, and the simulation was implemented on the VIVADO platform. Finally, the verification was performed by the companyfs LS-CPU- EXB-002 test box. The results showed the effectiveness of the designed multi-cycle CPU.
作者
柳成
荣静
LIU Cheng;RONG Jing(Guangling College ofYangzhou University,Yangzhou 22500)
出处
《软件》
2018年第8期40-44,共5页
Software
基金
扬州大学广陵学院资助项目(JGYB17012)