期刊文献+

WFTM-IP核设计与高速干涉图相位提取技术研究 被引量:2

High-speed phase extraction technique for interferograms by WFTM-IP core implementation
原文传递
导出
摘要 由于计算机操作系统多任务特性的局限性,无法满足数字干涉图分析技术的处理速度和操作的实时性,根据时-频域分析原理,提出了基于FPGA设计干涉图相位提取IP核,实现加窗傅里叶变换法(WFTM),WFTM-IP核包括数字干涉图的传输/存储模块、二维窗口傅里叶变换(2D-WFT)模块、频谱生成和相位提取等模块,从而完成高速干涉图相位提取。通过计算机仿真、云纹干涉和投影光栅实验测试,二维窗口傅里叶变换方法能够有效的缩短相位提取时间,提高了相位分布的提取速度,验证了WFTM-IP核的有效性和可靠性。 Due to the limitation of multitasking of computer operating system,the processing speed and the real-time operation of digital interferogram analysis cannot be satisfied. Based on the principle of time-frequency domain analysis,a high-speed phase extraction technique of interferograms is proposed by designing a IP core with FPGA( field programmable gate array) to implement the windowed fourier transform method( WFTM). The WFTM-IP core includes the transmission and storage module for digital interferograms,two dimensional windowed Fourier transform( 2 D-WFT) module,spectrum generation module and phase extraction module. Computer simulation and experimental results show that this propose technique can reduce the time and improve the speed of phase extraction,and verify the effectiveness and reliability of the WFTM-IP core.
出处 《电子测量与仪器学报》 CSCD 北大核心 2018年第6期124-130,共7页 Journal of Electronic Measurement and Instrumentation
基金 国家自然科学基金(61671008) 广西自然科学基金重点项目(2015GXNSFDA139003) 广西自动检测技术与仪器重点实验室基金(YQ14115、YQ17103)资助项目
关键词 数字干涉图 FPGA 加窗傅里叶变换 IP核 相位提取 digital Interferograms FPGA windowed Fourier transform IP core phase retrieval
  • 相关文献

参考文献8

二级参考文献71

  • 1翁嘉文,钟金钢.伸缩窗口傅里叶变换在三维形貌测量中的应用[J].光学学报,2004,24(6):725-729. 被引量:29
  • 2黄纯,江亚群.谐波分析的加窗插值改进算法[J].中国电机工程学报,2005,25(15):26-32. 被引量:107
  • 3白瑞林,江吕锋,王建.基于FPGA的模糊自整定PID控制器的研究[J].仪器仪表学报,2005,26(8):833-837. 被引量:23
  • 4GRANGETTO M, MAGLI E, MATINA M, et al. Optimization and implementation of the integer wavelet transform for image coding[J]. IEEE Trans. on Image Processing, 2002, 11(6): 596-604.
  • 5FERRETTI M, RIZZO D. A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme[J]. Journal of VLSI Signal Processing, 2001, 28: 165-185.
  • 6PREMKUMAR A B. An efficient VLSI architecture for the computation of 1-D discrete wavelet transform[J]. Journal of VLSI Signal Processing 2002, 31: 231-241.
  • 7TAI P L, LIU C T, WANG J SH. An integrated systolic array design for video compression[J]. Journal of VLSI Signal Processing, 2003, 33: 157-169.
  • 8LIMQUECO J C, BAYOUMI M A. A VLSI architecture for separable 2-D discrete wavelet transform[J]. Journal of VLSI Signal Processing, 1998, 18: 125-140.
  • 9MARTINA M, MASERA G, PICCININI C, et al. Novel JPEG 2000 compliant DWT and IWT VLSI implementation[J]. Journal of VLSI Signal Processing, 2003, 34: 137-153.
  • 10TESSIER R, BURLESON W. Reconfigurable computing for digital signal processing: A survey[J]. Journal of VLSI Signal Processing, 2001, 28: 7-27.

共引文献87

同被引文献9

引证文献2

二级引证文献10

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部