摘要
半导体工艺尺寸的急剧缩小使得提升数字电路容错能力变得尤为必要。传统的三模冗余会带来面积和功耗的巨大开销。本文提出一种信息冗余的容错设计方法,采用低密度奇偶校验(LDPC)码实现。由于数字电路中概率门模型的出错的概率ε与二进制对称信道(BSC)的噪声相似,因此将通信系统中的信道编译码方法应用到数字电路容错设计中。该设计在由逻辑门组成模块的输入输出端添加LDPC编译码。本文的LDPC码以1/2码率、816码长为例,并采用加权比特翻转(WBF)算法进行译码器设计。在ε∈(0. 0001,0. 1)范围内,对硬件冗余及信息冗余的容错结构进行了仿真和性能比较。误比特率(BER)曲线表明,当ε大于0. 05时,硬件冗余比信息冗余的BER低;反之,信息冗余的BER低于硬件冗余。
The miniaturization of semiconductor processes has rendered fault tolerance of digital circuits essential.The traiditional method such as triple modular redundancy(TMR)results in excessive consumption of area and power.In this paper,a fault-tolerant design method based on information redundancy is proposed for logic circuits,which is implemented by low density parity check(LDPC)code.Since the probability of error in the probability gate model in digital circuits is similar to that of the binary symmetric channel(BSC),the channel coding method in the communication system is applied to fault-tolerant design of digital circuits.The proposed design adds an LDPC encoder and decoder at the input and output of logic gates.The LDPC in this paper takes 816 code length and 1/2 code rate as example,and uses weighted bit flip(WBF)algorithm to design the decoder.Within the range of 0.0001 to 0.1,the performance of hardware-redundant and information-redundant fault-tolerance is simulated.The bit error rate(BER)curve shows that whenεis higher than 0.05,the hardware redundancy is lower than the information redundancy BER;conversely,BER of the information redundancy is lower than that of the hardware redundancy.
作者
王登超
班恬
薛文
Wang Dengchao;Ban Tian;Xue Wen(School of Electronic and Optical Engineering,Nanjing University of Science and Technology,Nanjing 210094)
出处
《高技术通讯》
EI
CAS
北大核心
2019年第1期69-77,共9页
Chinese High Technology Letters
基金
国家自然科学基金(61401205)
江苏高校"青蓝工程"资助项目
