摘要
功耗问题是制约集成电路设计的一个重要因素.分析了CMOS集成电路中功耗的来源,集成电路设计中功耗设计的目的,估算方法和功耗模型.研究模拟集成电路的特点和相应的功耗估计方法.针对采用环形振荡器的电荷泵锁相环,研究电荷泵锁相环的组成,各模块的工作原理及对功耗的贡献,提出了电荷泵锁相环系统级功耗估计模型.与实际测量结果相比,相对误差小于22%.该模型易于植入集成电路设计工具,可以对锁相环系统级设计提供功耗方面的参考,提高集成电路的设计质量.
Power is an important factor that restricts the design of Integrated Circuit (IC). The power origin in CMOS IC,the aim of power estimation in IC design,the estimation method,and the power model were analyzed. The characteristic of analog integrated circuit and the corresponding way for power estimation were studied. In order to distribute the power at system level, the construction of charge pump PLL,the principle of every module and the contribution to power were also studied. The power estimation model of charge pump PLL with ring oscillator was proposed at system level. The relative error is less than 22% when compared with the actual measurement. This model is easy to be integrated into design tools and can give guidance on power consumption for PLL at system level to improve the quality of Integrated Circuit design.
作者
魏建军
王振愿
陈付龙
刘乃安
李晓辉
WEI Jianjun;WANG Zhenyuan;CHEN Fulong;LIU Naian;LI Xiaohui(School of Telecommunications Engineering,Xidian University,Xi'an 710071,China;School of Mathematics and Computer Science,Anhui Normal University,Wuhu 241003,China)
出处
《湖南大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2019年第2期81-85,共5页
Journal of Hunan University:Natural Sciences
基金
国家自然科学基金面上项目(61572036)
陕西省自然科学基础研究计划面上项目(2017JM6052)
中央高校基本科研业务费专项资金资助
西安电子科技大学新教师创新基金项目(20199176405)~~
