摘要
面向较长LDPC码的硬件实现,在FPGA平台上实现了LDPC全并行译码器,实现变量节点功能,校验节点功能,提出了稀疏矩阵存储和FPGA指针操作的实现,并实现数据流的乒乓操作.通过Modelsim功能仿真表明,在500 MHz的时钟频率下,实现了在迭代最大次数为20次的条件下,译码速率可达240 Mbps.
For the hardware implementation of the longer LDPC,a LDPC decoding algorithm is complemented on the FPGA platform,which achieves the variable node function,the check node function,and which realizes the sparse matrix storage,the FPGA pointer operations and the ping-pong operation of data streams. The functional simulation of Modelsim shows that at the 500 MHz clock frequency,the decoding rate can reach 240 Mbps under the condition that the maximum number of iterations is 20.
作者
王海龙
郭大波
WANG Hai-long;GUO Da-bo(Physics Department,Lüliang University,Lishi Shanxi 033001,China;College of Physics and Electronic Engineering,Shanxi University,Taiyuan Shanxi 030006,China)
出处
《吕梁学院学报》
2019年第2期34-40,共7页
Journal of Lyuiang University
