摘要
电荷泵锁相环(charge pump phase-locked loop,CPPLL)作为频率合成器(frequency synthesizer,FS),广泛应用于接收机中来提供低杂散、低噪声、高频谱纯度的本振(local oscillator,LO)信号。电荷泵(charge pump,CP)作为关键模块之一,其存在的非理想效应以及失配会带来更高相位噪声影响锁相环(phase-locked loop,PLL)频率综合器输出本振的频谱纯度。基于台积电(Taiwan semiconductor manufacturing company,TSMC ) 0.18μm CMOS工艺,采用电流舵电荷泵结构并加入泄漏电流模块设计了一款低电流失配率、低相位噪声的电荷泵电路,较好地克服了传统电荷泵所存在的非理想效应,使整个电荷泵电路的相位噪声保持在较低的水平。利用Cadence Spectre对电荷泵的整体性能进行仿真。仿真结果表明,供电电压为1.8V时,电荷泵电流为31.71μA,最大相位噪声为-230dBc/Hz,在0.4~1.4V输出电压范围内最大电流失配率仅有0.22%。
Charge pump phase locked loop (CPPLL),as a frequency synthesizer,is widely used in receivers to provide local oscillator (LO) signals with low spurious,low noise and high frequency spectral purity.Charge pump (CP) is one of the key modules.Its non-ideal effect and mismatch will bring higher phase noise which will affect the spectral purity of the local oscillator output of phase locked loop (PLL) frequency synthesizer.Based on TSMC 0.18 μm CMOS technology,a charge pump circuit with low current mismatch rate and low phase noise is designed by using current steering charge pump structure and adding leakage current module.This circuit overcomes the non-ideal effect of traditional charge pump and keeps the phase noise of the whole charge pump circuit in a relatively low level.The overall performance of charge pump is simulated by Cadence Spectre.The simulation results show that when the supply voltage is 1.8 V,the charge pump current is 31.71 μA,the maximum phase noise is -230 dBc/Hz,and the maximum current mismatch rate is only 0.22% in the range of 0.4~1.4 V output voltage.
作者
王嘉齐
黄海生
李鑫
黄敏
WANG Jiaqi;HUANG Haisheng;LI Xin;HUANG Min(School of Electronic Engineering,Xi'an University of Posts and Telecommunication,Xi'an 710121,P.R.China)
出处
《重庆邮电大学学报（自然科学版）》
CSCD
北大核心
2019年第4期524-530,共7页
Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)
