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Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips

Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips
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摘要 A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield. A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores,which includes both the design-time mapping and run-time scheduling algorithms.Firstly,a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips.Then,during the run,one optimal task mapping solution is selected.Additionally,logical cores are mapped to physically available cores.Both core asymmetry and topological changes are considered in the proposed approach.Experimental results showthat the performance yield of the proposed approach is 96% on average,and the communication cost,power consumption and peak temperature are all optimized without loss of performance yield.
出处 《Journal of Beijing Institute of Technology》 EI CAS 2019年第3期497-509,共13页 北京理工大学学报(英文版)
关键词 process VARIATION TASK mapping FAULT-TOLERANT network-on-chips MULTI-CORE process variation task mapping fault-tolerant network-on-chips multi-core
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