期刊文献+

基于遗传粒子群算法的三维芯片热布局优化 被引量:4

Optimization of 3D Stacking Chip Thermal Layout Based on Genetic Particle Swarm Algorithm
下载PDF
导出
摘要 三维叠层芯片是由多层芯片堆叠而成,其热效应与散热问题尤为突出。采用遗传粒子群算法对三维叠层芯片的热布局进行优化,研究了该芯片的功率以及个数对热布局的影响。仿真结果表明:使用遗传粒子群算法的热布局的优化精度较高,经过优化后的三维叠层芯片的温度分布更加均匀,最高温度以及温度梯度都有显著降低;三维叠层芯片的功率越高,以及堆叠的芯片个数越多,热布局优化的结果就越明显。 Three-dimensional stacking chips are stacked by multi-layer chips,so their thermal effects and heat dissipation problems are particularly prominent.The thermal layout of three-dimensional stacking chips is optimized by genetic particle swarm optimization.The influence of the power and number of the stacking chips on the thermal layout is studied.The simulation results show that the genetic particle swarm optimization algorithm has high optimization accuracy.The temperature distribution of the optimized threedimensional stacked chips is more uniform,and the maximum temperature and temperature gradient decrease significantly.The higher the power of the three-dimensional stacked chips and the more stacked chips,the more obvious the thermal layout optimization results are.
作者 杨志清 潘中良 YANG Zhiqing;PAN Zhongliang(School of Physics and Telecommunications Engineering,South China Normal University,Guangzhou510006,China)
出处 《电子工艺技术》 2019年第5期249-252,260,共5页 Electronics Process Technology
基金 广州市科技计划项目(201904010107) 广东省科技计划项目(2016B090918071)
关键词 三维堆叠芯片 热布局 热分析 遗传粒子群算法 three-dimensional stacking chip thermal layout thermal analysis genetic particle swarm algorithm
  • 相关文献

参考文献2

二级参考文献14

  • 1Chu Chris C N, Wong D F. A matrix synthesis approach to thermal placement [A]. In: Proceedings of International Symposium on Physical Design, Napa Valley, 1997. 163~ 168
  • 2Tsai Ching-Han, Kang Sung-Mo. Cell-level placement for improving substrate thermal distribution [J]. Computer-Aided Design of Integrated Circuits and Systems, 2000, 19(2): 253~266
  • 3Chen G, Sapatnekar S S. Partition-driven standard cell thermal placement [A]. In: Proceedings of International Symposium on Physical Design, Monterey, 2003. 75~80
  • 4Tang Man Chak, Carothers J D. Consideration of thermal constraints during multi-chip module placement [J ]. Electronics Letters, 1997, 33(12): 1043~1045
  • 5Beebe C, Carothers J D, Ortega A. Object-oriented thermal placement using an accurate heat model [A]. In: Proceedings of the 32nd Annual Hawaii International Conference on System Sciences, Hawaii, 1999. 1~10
  • 6Nakatake S, Fujiyoshi K, Murata H, et al. Module placement on BSG structure and IC layout applications [A]. In:Proceedings of International Conference on Computer Aided Design, San Jose, 1996. 484 ~491
  • 7Murata H, Fujiyoshi K, Nakatake S, et al. Rectangle-packing based module placement [A]. In: Proceedings of International Conference on Computer Aided Design, San Jose, 1995. 472~479
  • 8Hong Xianlong, Huang Gang, et al. Corner block list: An effective and efficient topological representation of non-slicing floorplan [A]. In: Proceedings of International Conference on Computer Aided Design, San Jose, 2000. 8~ 12
  • 9Guo P N, Cheng C K, Yoshimura T. An O-Tree representation of nonslicing floorplan and its applications [A]. In: Proceedings of Design Automation Conference, New Orleans, 1999. 268~273
  • 10Chang Y C, Chang Y W, Wu G M, et al. B*-trees: A new representation for non-slicing floorplans [A]. In: Proceedings of Design Automation Conference, Los Angeles, 2000. 458~463

共引文献77

同被引文献42

引证文献4

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部