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IXP 2400网络处理器低功耗技术应用研究 被引量：1

A Study on the Application of Low Power Technologies of IXP2400 Network Processor
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摘要 文章从软件低功耗优化角度,结合IXP2400网络处理器中XScalecore处理器体系结构的低功耗技术特点,在SimWattch模拟平台上,就频率动态调整和程序设计语言不同结构成分对应用程序运行功耗的影响进行了模拟和分析,通过对一组Banchmark程序的模拟,结果表明在编译系统、操作系统或应用程序设计中采用这些低功耗优化技术设计可降低至少23%以上的运行功耗。 From the software aspect for low power optimization,the architecture of XScale core in IXP2400network pro-cessor is simulated on SimWattch.The effect of dynamic scalable frequency and components of programming language on the power consumption of running an application is analyzed in this paper.The results of simulating a set of benchmark programs demonstrates that the power consumption can be decreased at least above23%by using these technologies for low power in the design of the compiler,operating system or application program.
作者 赵荣彩 唐志敏 邵洁
机构地区 中国科学院计算技术研究所
出处 《计算机工程与应用》 CSCD 北大核心 2002年第22期71-73,127,共4页 Computer Engineering and Applications
基金 国家863高技术研究发展计划的资助(编号:2001AA111070)
关键词 IXP2400网络处理器 低功耗技术 体系结构 微处理器 并行处理 Keyw ords :Low Power,Architecture,Compile,Simulation
分类号 TP332 [自动化与计算机技术—计算机系统结构]
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参考文献9

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同被引文献12

  • 1YEONG J H,RAO X M,SHAJAN M R. 802.11 a MAC layer:firmware/hardware co-design[A].2003.1923-1928.
  • 2BUCAILLE I,TONNERRE A,OUVRY L. MAC layer design for UWB LDR systems:PULSERS proposal[A].2007.277-283.
  • 3FUJISAWA T,HASEGAWA J,TSUCHIE K. A single-chip 802.11a MAC/PHY with a 32-b RISC processor[J].IEEE Journal of Solid-State Circuits,2003,(11):2001-2009.doi:10.1109/JSSC.2003.818135.
  • 4CHANG Chih-yung,SHIH Kuei-ping,LEE Shih-chieh. On improving network connectivity by power-control and code-switching schemes for multihop packet radio networks[A].IEEE,2005.540-545.
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  • 6CHRISTENSENA K J,GUNARATNE C,NORDMAN B. The next frontier for communications networks:power management[J].Computer Communications,2004,(18):1758-1770.doi:10.1016/j.comcom.2004.06.012.
  • 7LEE Seong-won,GAUDIOT Jean-luc. Throttling-based resource management in high performance multithreaded architectures[J].IEEE Transaction on Computer,2006,(09):1142-1152.doi:10.1109/TC.2006.154.
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  • 9YAP K S,BOEY K H. Clock gating methodology for high performance network processor in 90 nm[A].IEEE,2004.
  • 10XIE Jian-yang,TANG Xiang-long,LI Tie-cai. low power design based on neural network forecasting for interconnection networks[A].2006.2979-2983.

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计算机工程与应用
2002年 第22期

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