摘要
分析了宽频带、低相噪锁相频率合成器的设计方法 ,并给出宽频带、低相噪频率合成器的设计方案 .采用分段混频分频 PL L 频率合成器 ,实现了基于大规模锁相集成芯片 Q32 36的宽带锁相频率合成器 .其输出频率为10 0 0～ 2 16 0 MHz,频率步进 2 0 MHz,相位噪声优于 - 98d B/ Hz(偏离载频 1k Hz处 ) ,杂散抑制优于 6 0 d B,输出功率 Pm>8d B.测试结果表明 ,该设计有效地扩展了信号带宽 ,达到了极低的相位噪声 .
Methods of design in wideband, low phase noise frequency synthesizers were analyzed. A scheme of synthesizer design is proposed, in which a mixing-PLL frequency synthesis technique is used, thus realizing wide-range PLL frequency synthesizer applying the chip Q3236. The scheme has a frequency range of 1 000～2 160 MHz, with a frequency step of 20 MHz, phase noise≥ -95 dB/Hz (offset 1 kHz from carrier), spurious free dynamic range 60 dB, P m≥8 dB. All test results proved that it is an effective method to expand the bandwidth and that it achieves successfully ultra-low phase noise.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2002年第5期643-645,共3页
Transactions of Beijing Institute of Technology
基金
国家"九五"预研项目
