摘要
在译码器领域,研究一种低密度奇偶校验码LDPC的解码方法。研究发现,存储量仅是和积算法的一半左右,在达到同样的BER性能时,迭代次数也是和积算法的一半左右,在面积和处理速度方面达到折中。根据DTMB LDPC码的结构特点,在综合考虑性能和硬件实现两方面,提出了一种简化的解码方法以及LLR运算的计算方法,在性能上和原算法等价,且其硬件实现资源比原算法可减少较多的存储容量。
In the field of decoders, a low-density parity-check LDPC decoding method is studied. It is found that the storage capacity is only about half of the sum-product algorithm. When the BER performance is the same, the number of iterations is about half of the sum-product algorithm, and the tradeoff between area and processing speed is achieved. According to the structure characteristics of DTMB LDPC codes, considering both performance and hardware implementation, a simplified decoding method and a calculation method of LLR operation are proposed in this paper, which are equivalent to the original algorithm in performance, and the hardware implementation resources can reduce more storage capacity than the original algorithm.
作者
钟培峰
刘小同
张笑
ZHONG Peifeng;LIU Xiaotong;ZHANG Xiao(Jingchen Semiconductor Shanghai Co.,Ltd,Shanghai 201203,China.)
出处
《集成电路应用》
2019年第8期69-71,共3页
Application of IC
基金
上海市经济和信息化委员会软件和集成电路产业发展专项基金(1500303)SoC芯片的研发和产业化
关键词
集成电路
解码方法
低密度奇偶校验
integrated circuit
decoding method
low density parity check
