摘要
AES是现有的一种抗攻击能力强、加密速度快以及可移植性好的加密算法。在FPGA上实现AES算法可以更快地处理数据。为了提高整体系统的运行速度,在优化设计中采用全流水的技术来实现算法,并对S-box进行优化。S-box是AES算法中唯一的非线性单元,在进行加密、解密尤其是在字节替换过程时,需要分别执行S-box和逆S-box,一般使用查表来进行操作,这样会占用大量的资源,所以对S-box进行优化是对整个算法优化的最重要的步骤。最终使用Modelsim对设计结果进行仿真然后使用Quartus进行总体综合。
AES is an existing encryption algorithm with strong anti-attack capability,fast encryption speed and good portability.Implementing AES algorithms on FPGA can process data faster.In order to improve the operating speed of the overall system,we adopt a full-flow technology to implement the algorithm in the process of optimization and design.We optimized the S-box.S-box was the only nonlinear unit in AES algorithm.In the process of encryption and decryption,especially in the byte replacement process,it was necessary to separately execute the S-box and the inverse S-box.Generally,the look-up table was used to do the operation,which occupied a large amount of resources,so optimizing the S-box was the most important step in optimizing the entire algorithm.Modelsim was applied to simulate the design results and Quartus was used for synthesis.
作者
刘宇峰
许向阳
苏浩
耿艳香
刘婷
Liu Yufeng;Xu Xiangyang;Su Hao;Geng Yanxiang;Liu Ting(School of Information Science and Engineering,Hebei University of Science and Technology,Shijiazhuang 050000,Hebei,China;School of Information and Engineering,Tianjin University of Commerce,Tianjin 300134,China)
出处
《计算机应用与软件》
北大核心
2020年第1期267-270,297,共5页
Computer Applications and Software
基金
天津市企业科技特派员项目(18JCTPJC66900)
