摘要
基于南京电子器件研究所的0.7μm InP HBT工艺设计了一种数据转换速率达到50 Gb/s的1:4量化降速芯片。该芯片同时将前端高速高灵敏度比较器与一个1:4分接器集成到单芯片中,能够直接一次性实现对2~18 GHz带宽的模拟输入信号的可靠接收和降速处理,输入信号灵敏度在芯片最高工作速率下达到1 mV,工作电压3.3 V,芯片功耗1.5 W,最高数据转换速率达到50 Gb/s,输出数据信号与时钟信号幅值均达到200 mV。
Based on the 0.7μm InP HBT process of Nanjing Electronic Device Research Institute,a 1:4 quantized speed-down chip with a data conversion rate of 50 Gb/s is designed.At the same time,the chip integrates a front-end high-speed and high-sensitivity comparator with a 1:4 demultiplexer,so it is possible to directly achieve reliable reception and speed-down processing of analog input signals with a bandwidth of 2~18 GHz.The sensitivity of the input signal reaches 1 mV at the maximum operating rate of the chip,the operating voltage is 3.3 V,and the chip consumes 1.5 W.The highest data conversion rate reaches 50 Gb/s,and the amplitude of the output data signal and the clock signal reach 200 mV.
作者
周浩
张有涛
Zhou Hao;Zhang Youtao(Nanjing Electronic Devices Institute,Nanjing 210016,China;Nanjing GuoBo Electronics Co.,Ltd.,Nanjing 210016,China;Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing 210016,China)
出处
《电子技术应用》
2020年第6期45-50,共6页
Application of Electronic Technique
关键词
高速电路
比较器
分接器
树型结构
InP
HBT
高灵敏度
high-speed circuits
comparator
demultiplexer
tree structure
InP hetero-junction bipolar transistor
high sensitivity
