摘要
为节省FPGA(Field Programmable Gate Array)升级工作的时间和成本,设计了一种利用UART(Universal Asynchronous Receiver/Transmitter)替代传统JTAG(Joint Test Action Group)方式升级的FPGA程序方法,该设计主要由Xilinx FPGA、UART芯片、Flash芯片和串口连接线等组成。通过将MicroBlaze处理器、ICAP(Internal Configuration Access Port)、IP(Intellectual Property)核及UART控制模块等集成在FPGA芯片中实现可编程片上系统的搭建。同时采用MultiBoot双镜像技术,实现了即使在更新失败的情况下,依旧可加载备份镜像保证系统正常工作,以此保证设计的稳定性。实验结果表明,此设计可以替代传统FPGA升级方法,节省升级工作的时间和成本。本设计具有更新效率高、维护成本低、稳定性高等优点,且可用于FPGA远程更新。
In order to save the time and cost of FPGA(Field Programmable Gate Array)upgrade,we design a FPGA program method that uses UART(Universal Asynchronous Receiver/Transmitter)to replace the traditional JTAG(Joint Test Action Group)method.The design is mainly composed of Xilinx FPGA,UART chip,Flash chip and serial port connection line.By integrating the MIcroBlaze processor,ICAP(Internal Configuration Access Port),IP(Intellectual Property)core and UART control module into the FPGA chip,the system on the programmable chip is set up.At the same time,MultiBoot double mirror technology is adopted to achieve that even if the update fails,the backup image can still be loaded to ensure the normal work of the system,so as to ensure the stability of the design.Experimental results show that this design can replace the traditional FPGA upgrade method and save the upgrade time and cost.This design has the advantages of high update efficiency,low maintenance cost,high stability,and can be used for FPGA remote update.
作者
常亮
毕今朝
蒋佳奇
CHANG Liang;BI Jinzhao;JIANG Jiaqi(The Thirty Second Research Institute,China Electronics Technology Group Corporation,Shanghai 201808,China;College of Electronic Science and Engineering,Jilin University,Changchun 130012,China)
出处
《吉林大学学报（信息科学版）》
CAS
2020年第3期286-290,共5页
Journal of Jilin University（Information Science Edition）
基金
国家自然科学基金资助项目(61674068,61734001)。
关键词
FPGA芯片
UART芯片
MultiBoot双镜像
可编程片上系统
field programmable gate array(FPGA)
universal asynchronous receiver/transmitter(UART)
MultiBoot
programmable system-on-chip(PSOC)
