摘要
全数字锁相环(All-digital Phase Locked Loop,ADPLL)中时间数字转换器(Time-to-Digital Converter,TDC)用于测量数控振荡器(Digitally Controlled Oscillator,DCO)输出时钟和参考时钟之间分数相位差,其分辨率越高,环路的相位噪声特性越好。为了提升TDC的测量分辨率,提出了一种对工艺偏差不敏感的环形互连线插值的TDC结构。本文首先给出了基于互连线插值TDC的系统结构,然后提出了一种工艺偏差不敏感的互连线结构实现等延时方法,并给出了环形的版图布局方案,最后利用仿真对提出的等延时实现方法进行验证。实验结果表明:该方法即使是在0.18μm CMOS工艺下也能将TDC的分辨率提高至皮秒级。
[Background]In the all-digital phase-locked loop(ADPLL),the time-to-digital converter(TDC)is used to measure the fractional phase difference between the digital controlled oscillator(DCO)output clock and the reference clock.The higher the resolution of TDC,the better the phase noise characteristics of the loop.[Purpose]This study aims to improve the phase noise of ADPLL and enhance the resolution of TDC by using interconnect delay.[Methods]Firstly,the system structure of TDC based on interconnect line interpolation was proposed.Then,an interconnect delay method with process deviation insensitivity was implemented to realize the equal delay mechanism,and a layout structure of the ring was discussed.[Results]The experimental results show that the resolution of TDC designed by the proposed method is up to 5.35 ps in 0.18μm CMOS process.[Conclusions]The design method of TDC based on interconnect interpolation proposed in the paper can improve the resolution.
作者
周郭飞
杨宏
ZHOU Guofei;YANG Hong(First Research Institute of the Ministry of Public Security,Beijing 100044,China)
出处
《核技术》
CAS
CSCD
北大核心
2020年第7期40-46,共7页
Nuclear Techniques
基金
十三五国家重点研发计划项目资助。
