期刊文献+

基于FPGA信号传输两级数字多相滤波器的研究 被引量:1

Research on Two-stage Digital Polyphase Filter Based on FPGA Signal Transmission
下载PDF
导出
摘要 为满足信号传输不同分辨率要求,论文基于多相滤波器组通过无盲区的均匀信号划分实现了两级数字信息传输通道化[1],给出了基于FPGA实现的并行结构和多相分支折叠结构。第一级信道化对整个传输模块瞬时带宽进行粗划分,第二级信道化对一级信道化的子信道带宽进行细划分,提高了信号传输的频率分辨率。最终对系统进行仿真测试,验证了设计的正确性合理性。 To meet the different resolution requirements of channelized receivers,basing on the polyphase filter bank and uni⁃form channel partition without blind zone,two-level digital channelization is realized.The structrue of paralleling and mult-phase branch folding are respectively employed in the FPGA.In this dissertation,an approach is studied to realize a high-performance wideband digital receiver based on two-level channelization through uniform channel division without blind zone.The first level al⁃lows coarse division towards the whole instantaneous bandwidth of the receiver.The further division of sub-channel of the former is achieved in the second level.The frequency resolution of each channel is improved.Eventually,the system is simulated and tested,it is verified that the design is rational and efficient.
作者 何俊峰 赵红阳 HE Junfeng;ZHAO Hongyang(Huazhong Institute of Electro-Optics,Wuhan National Laboratory for Optoelectronics,Wuhan 430223)
出处 《舰船电子工程》 2020年第10期164-167,共4页 Ship Electronic Engineering
关键词 FPGA 数字信号 两级滤波 多相滤波 FPGA digital signal two-level filter polyphase filter
  • 相关文献

参考文献6

二级参考文献42

  • 1管吉兴.FFT的FPGA实现[J].无线电工程,2005,35(2):43-46. 被引量:13
  • 2陈志斌.一种可重构DFT/DHT/DCT/DST结构的设计[J].湘潭师范学院学报(自然科学版),2005,27(4):32-35. 被引量:1
  • 3蒋宗明,唐斌,吴伟.基于DFT滤波器组的多信号高效数字下变频[J].电子科技大学学报,2005,34(6):743-746. 被引量:5
  • 4杨旭霞,归琳,余松煜.3 780点FFT处理器的研究[J].电视技术,2005,29(11):32-34. 被引量:7
  • 5胡广书.数字信号处理:理论、算法与实现[M].北京:清华大学出版社,2002:481-484.
  • 6[美]贝斯.数字信号处理的FPGA实现[M].刘凌,胡永生,译.北京:清华大学出版社,2003.
  • 7Atmel. AT84AD001B Smart ADC Datasheet[EB/OL]. www. atmel, com.
  • 8M. J. Ready, M. L. Downey, L. J. Corbalis. Automatic noise floor spectrum estimation in the presence of signals [ C ]. Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers, 1997,1 : 877- 881.
  • 9M. Adhiwiyogo. Virtex-4 High-Speed Dual Data Rate LVDS Transceiver [ EB/OL]. http://www, xilinx, com/support/documentation/application_notes/xapp705, pdf,2005- 10-8.
  • 10N. Sawyer. 1:7 Deserialization in Spartan-3E/3A FPGAs at Speeds up to 666 Mbps [ EB/OL ]. http ://www. xilinx, corn/ support / documentation / application_notes / xapp485 . pdf ,2006-11-10.

共引文献54

同被引文献3

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部