摘要
为了缓解LDMOS中比导通电阻与击穿电压之间的矛盾关系,提出了一种具有2层堆叠结构的LDMOS器件。该结构由2个独立的LDMOS器件堆叠形成,因而在此器件导通时,2个LDMOS的漂移区形成了2条电流路径,且由于上层LDMOS的衬底能够将2条电流路径隔离,从而使得2条路径上的电流独立工作而不互相干扰,进而提高器件的导通电流。另外,上层LDMOS的漂移区能够同时被其衬底以及内部的P埋层和P浮空层耗尽,下层LDMOS的漂移区也能同时被上下两层LDMOS的衬底耗尽,于是上下两层LDMOS的漂移区浓度得到了较大提升,两层堆叠LDMOS器件的比导通电阻也获得了改善。在上下两层LDMOS的界面处分别引入P-top区和N-top区,可有效降低下层LDMOS漏源附近高的电场强度,从而防止其在这两端提前发生击穿现象,继而提高了两层堆叠LDMOS器件的击穿电压。使用半导体二维仿真软件对器件的结构参数进行模拟验证。结果表明,两层堆叠LDMOS的击穿电压为356 V,比导通电阻为13.56 mΩ·cm^(2),与常规LDMOS相比,分别改善了26.2%和71.6%。
In order to alleviate the conflicting relationship between the specific on resistance and breakdown voltage in LDMOS,an LDMOS device with a two-layer stacked structure is proposed.This structure is formed by stacking two independent LDMOS devices,thus the drift regions of the two LDMOS form two current paths when this device is turned on,and the substrate of the upper LDMOS is able to isolate the two current paths so that the currents on the two paths work independently without interfering with each other,thereby increasing the on-state current of the device.In addition,the drift region of the upper LDMOS can be depleted by its substrate and the internal P-buried layer and P-floating layer at the same time,and the drift region of the lower LDMOS can be depleted by the substrates of the upper and lower LDMOS layers at the same time,so the drift region concentration of the upper and lower LDMOS layers is better improved,and the specific on-resistance of the two-layer stacked LDMOS devices is improved accordingly.The introduction of P-top and N-top regions at the interface between the upper and lower LDMOS layers can effectively reduce the high electric field intensity near the drain source of the lower LDMOS,thus preventing its early breakdown at these two ends and subsequently increasing the breakdown voltage of the two-layer stacked LDMOS devices.The structural parameters of the device are simulated and verified by using the semiconductor simulation software.The simulation results show that the breakdown voltage of the two-layer stacked LDMOS is 356 V and a specific on-resistance of 13.56 mΩ·cm^(2),which is 26.2%and 71.6%better than that of the conventional LDMOS,respectively.
作者
党天宝
李琦
黄洪
姜焱彬
王磊
DANG Tianbao;LI Qi;HUANG Hong;JIANG Yanbin;WANG Lei(School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China)
出处
《桂林电子科技大学学报》
2021年第2期106-112,共7页
Journal of Guilin University of Electronic Technology
基金
国家自然科学基金(61464003,61874036)
广西自然科学基金(2018GXNSFAA281201)
桂林电子科技大学研究生教育创新计划(2020YCXS033)。
