摘要
在传统二端忆阻器的理论基础上,提出了一种四端忆阻器的模型.该器件的4个端口分别对应于MOS场效应晶体管的栅、源、漏和衬底4个极,可以代替数字电路中的MOS晶体管实现电路功能.利用Verilog-A对该模型的电学特性进行了描述,在Hspice软件环境中利用该模型构建了与非、或非等逻辑电路以及1 bit数据的1R-1R随机存取电路,并搭建外围电路对其进行了功能验证,在仿真层面实现了四端忆阻器在数字电路方面的简单应用,实验结果符合预期.作为一种纳米器件,与MOS晶体管相比,四端忆阻器的尺寸更小、功耗更低.在CMOS工艺尺寸渐渐趋于极限的今天,对四端忆阻器的应用是一个具有一定合理性的发展方向.
To replace the MOSFET in digital circuits,a four-terminal memristor model is proposed based on the traditional two-terminal memristor,whose four terminals respectively correspond to the gate,source,drain and substrate of the MOSFET.The model described by Verilog-A is used to construct NAND,NOR,etc.logic gate circuits,1 R-1 R random access circuit of 1 bit data in the software environment of Hspice.And the simple application of four-terminal memristor in digital circuits is realized at the simulation level.The experimental results are in line with expectations.As a kind of nanodevice compared with the MOSFET,the four-terminal memristor has greater advantages in terms of small size and low power consumption.With the size of CMOS process gradually approaching the limit,the application of the four-terminal memristor is a reasonable direction.
作者
张章
魏亚东
葛志恒
闫林
曾剑敏
刘钢
Zhang Zhang;Wei Yadong;Ge Zhiheng;Yan Lin;Zeng Jianmin;Liu Gang(School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230009;School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240)
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2021年第7期1126-1131,共6页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金(U19A2053,61674049)
国家重点实验室开放课题(2019KF003)
中国科学院重点实验室开放课题(IIMDKFJJ-19-04)
中央高校基本科研业务费项目(JZ2020YYPY0089)。
关键词
四端忆阻器
逻辑电路
随机存取电路
纳米器件
低功耗
four-terminal memristor
logic circuit
random access circuit
nanodevice
low power consumption
