摘要
阐述背照式图像传感器(Backside Illumination,BSI)芯片,将硅片减薄后,在photodiode背面搭建CF及Micro Lens,光线由背面射入,增大了光电元件感光面积,减少了光线经过布线时的损失,以此可以大幅提高CIS在弱光环境下的感光能力。在华力BSI芯片流程中,钨刻蚀工艺是影响芯片光学信号噪音(RTS)的关键步骤,其关键尺寸及氧化层厚度的稳定性决定了产品质量的稳定性。但整个钨刻蚀工艺流程极长,其中多道工序对钨塞的形貌有显著影响,且依赖钨刻蚀工艺的关键尺寸等监控参数评估其工艺稳定性,给钨刻蚀工艺线上参数的管控带来诸多影响因子。通过工艺窗口实验,线上异常数据分析等方式,系统评估了钨刻蚀工艺线上监控参数与产品质量的关系,并详细讨论了BSI钨刻蚀整段工艺流程中前道工序对钨刻蚀后线上监控参数的影响,提出了各道工艺的影响机理及其对产品质量的影响因素。数据显示当钨刻蚀工艺的关键尺寸小于60nm时晶片边缘开始出现DINU的失效,当氧化层厚度小于850?时同样有晶片边缘DINU失效的风险。另外,钨刻蚀工艺后在晶片表面存在钨残留会导致一定的产品良率损失。而在整段钨刻蚀工艺流程中,硅沟槽的湿法刻蚀、金属钨沉积和钨的研磨步骤皆会对钨刻蚀后的关键尺寸造成影响,氧化层沉积厚度会对钨刻蚀后氧化层厚度造成接近1:1的影响。量产过程中主要的良率损失均来源于关键尺寸小于60nm后的DINU失效。
This paper describes the back illuminated image sensor(BSI) chip. After the silicon wafer is thinned, CF and micro lens are built on the back of photodiode. The light is injected from the back, which increases the photosensitive area of the photoelectric element and reduces the loss of light when it passes through the wiring, so as to greatly improve the photosensitive ability of CIS in weak light environment. In HLMC BSI chip process, tungsten etching process is the key step to affect the optical signal noise(RTS). The stability of the key size and oxide thickness determines the stability of product quality. However, the whole tungsten etching process is very long, in which multiple processes have a significant impact on the morphology of the tungsten plug, and the process stability is evaluated by monitoring parameters such as the key dimensions of the tungsten etching process, which brings many factors to the control of parameters on the tungsten etching process line. The relationship between on-line monitoring parameters of tungsten etching process and product quality was systematically evaluated by means of process window experiment and On-line abnormal data analysis. The influence of the previous process on on-line monitoring parameters after tungsten etching was discussed in detail. The influence mechanism of each process and its influencing factors on product quality were proposed. The data show that when the critical size of the tungsten etching process is less than 60 nm, Dinu failure begins to appear at the edge of the wafer, and when the thickness of the oxide layer is less than 850? There is also the risk of Dinu failure at the chip edge. In addition, the existence of tungsten residue on the wafer surface after tungsten etching process will lead to a certain yield loss. In the whole process of tungsten etching, wet etching of silicon groove, deposition of tungsten and grinding of tungsten will affect the key dimensions of tungsten after etching, and the thickness of oxide layer will affect the thickness of oxide layer by nearly 1:1. The main yield loss in mass production process comes from Dinu failure when the critical size is less than 60 nm.
作者
张钱
昂开渠
ZHANG Qian;ANG Kaiqu(Shanghai Huali Integrated Circuit Manufacturing Co.,Ltd.,Shanghai 201203,China)
出处
《集成电路应用》
2021年第7期43-47,共5页
Application of IC
基金
上海市经济和信息化委员会软件和集成电路产业发展专项基金(1500204)。
