摘要
针对采用级联延时结构的高频延时线存在损耗较高的问题,提出了一种采用0.18μm CMOS工艺的宽带延时线集成电路芯片,其性能指标为5 bit延时控制,120 ps最大延时,3.9 ps延时分辨率。该延时电路采用二阶全通网络(all pass networks,APN)作为延时结构,并设计了一种新的群延时交错方法。该方法利用二阶APN群延时频率响应的峰值特性,从单个APN电路中提取更多的群延时,可以用较少的无源二阶APN电路实现更高的群延时,同时又能降低所设计延时线的插入损耗。采用0.18μm CMOS工艺进行了具体实现和性能测试。结果表明,该电路芯片面积为1.2 mm×2.7 mm,与现有集成延时线相比,所提电路的插入损耗更低。在8 GHz~18 GHz的频率范围内,插入损耗为12.6 dB~20.5 dB,均方根延时误差小于3.3 ps。
Aiming at the problem of high loss of delay line with cascaded delay structure,a broadband delay line integrated circuit chip with 0.18μm CMOS process is proposed,and its performance indexes are 5 bit delay control,120 ps maximum delay and 3.9 ps delay resolution.In this delay circuit,APN(all pass networks)is used as the delay structure,and a new group delay interleaving method is designed.The method uses the peak characteristics of the second-order APN group delay frequency response to extract more group delays from a single APN circuit,which can achieve higher group delays with fewer passive second-order APN circuits and reduce the insertion loss of the designed delay lines.0.18μm CMOS process is used to realize and test the performance.The results show that the chip area of the circuit is 1.2×2.7 mm^(2),and the insertion loss of the proposed circuit is lower than that of the existing integrated delay line.In the frequency range of 8 GHz~18 GHz,the insertion loss is 12.6 dB~20.5 d B,and the root mean square delay error is less than 3.3 ps.
作者
张明
徐琴
ZHANG Ming;XU Qin(School of Software,Chengdu Polytechnic,Chengdu Sichuan 610041,China;College of Mobile Telecommunications,Chongqing University of Posts and Telecom,Chongqing 401520,China)
出处
《电子器件》
CAS
北大核心
2021年第5期1041-1046,共6页
Chinese Journal of Electron Devices
基金
重庆市教委科学技术研究项目(KJZD-K201902401)。
关键词
延时电路
无源延时线
二阶全通网络
低插入损耗
群延时
delay circuit
passive delay line
second-order all-pass network
low insertion loss
group delay
