期刊文献+

三维集成电路集成硅通孔的应力应变研究 被引量:2

Reliability Research of Integrated Through Silicon Vias in 3D Integrated Circuits-Stress and Strain Research
下载PDF
导出
摘要 采用有限元模拟法研究三维集成电路集成中硅通孔结构在热循环载荷条件下的失效行为,对硅通孔结构的应力应变进行分析。结果表明,硅通孔结构在热循环载荷下顶部Cu焊盘角落附近的SiO;层处具有最大的应力与应变,这表明硅通孔结构中最易失效位置在顶部Cu焊盘角落附近Cu和SiO;的界面处。试验结果与模拟分析一致,进一步验证了模拟结果对硅通孔结构最易失效位置分析的可靠性。 The finite element simulation method is used to study the failure behavior of TSV structures in3D integrated circuits under thermal cyclic loading conditions,and the stress and strain of TSV structures are analyzed.The results show that the maximum deformation amount of the TSV structure under thermal cyclic loading is located at the center of the top Cu pad,and the SiO;layer near the corners of the top Cu pad has the largest stress and strain,which indicates that the TSV structure in the The most vulnerable location is at the interface of Cu and SiO;near the corner of the top Cu pad.The experimental results are consistent with the simulation analysis,which further verifies the reliability of the simulation results for the analysis of the most vulnerable location of the TSV structure.
作者 苏鹏 徐鹏程 秦进功 王东 田野 SU Peng;XU Pengcheng;QIN Jingong;WANG Dong;TIAN Ye(Henan University of Technology,Zhengzhou 450000,China)
机构地区 河南工业大学
出处 《河南科技》 2022年第4期51-54,共4页 Henan Science and Technology
关键词 硅通孔 三维封装 热循环 可靠性 有限元分析法 through silicon via 3D packaging thermal cycling reliability finite element analysis method
  • 相关文献

参考文献7

二级参考文献29

  • 1盛重,薛松柏,张亮,皋利利.引线间距对QFP焊点的可靠性影响的有限元分析[J].焊接学报,2008,29(5):85-88. 被引量:9
  • 2Kim Y,Kang S K,Kim S D,et al.Wafer warpageanalysis of stacked wafers for 3D integration [ J].Microelectron.Eng.,2012,89:46-49.
  • 3Ryu S,Lu K,Zhang X,et al.Impact of near-surfacethermal stresses on interfacial reliability of through-silicon-vias for 3-D interconnects![J].IEEE Trans,onDevice and Materials Reliability? 2011,11(1):35-43.
  • 4Sun P,Andersson C,Wei X,et al.High temperatureaging study of intermetallic compound formation of Sn-3.5Ag and Sn-4.0Ag-0.5Cu solders on electroless Ni(P) metallization [J].J.Alloys and Compounds,2006,425(1/2):191-199.
  • 5Liu X,Chen Q,Dixit P,et al.Failure mechanisms andoptimum design for electroplated copper through-silicon vias ( TSV) [C]//Proc.59th ElectronicComponents and Technol.Conf.,2009:624-629.
  • 6Haq J,Vogt B D,Raupp G B,et al.Finite elementmodeling of temporary bonding systems for flexiblemicroelectronics fabrication[J].Microelectron.Eng.,2012,94:18-25.
  • 7Read D T,Cheng Y W,Geiss R.Morphology,microstructure,and mechanical properties of a copperelectrodeposit[J],Microelectron.Eng.,2004,75(1):63-70.
  • 8Shen L C,Chien C W,Cheng H C,et al.Developmentof three-dimensional chip stacking technology using aclamped through-silicon via interconnection [ J].Microelectron.Reliability,2010*50(4):489-497.
  • 9郎鹏,高志方,牛艳红.3D封装与硅通孔(TSV)工艺技术[J].电子工艺技术,2009,30(6):323-326. 被引量:23
  • 10侯珏,陈栋,肖斐.硅通孔互连技术的可靠性研究[J].半导体技术,2011,36(9):684-688. 被引量:4

共引文献26

同被引文献19

引证文献2

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部