摘要
在超高速数字信号处理中,受限于硬件处理最高运行时钟的限制,一般需要对输入的单路数据进行并行化处理。利用多相分解技术来对高速数字FIR滤波器的并行化进行实现,同时针对FIR滤波器多相分解之后系数不再满足对称性这一问题,构建其对称性系数因子。在多相分解技术的FPGA实现中,可以减少一半的乘法器的使用,可有效优化FPGA资源量的消耗。
In ultra-high-speed digital signal processing,due to the limitation of the maximum operating clock for hardware processing,it is generally necessary to parallelize the input single-channel data.The polyphase decomposition technique is used to realize the parallelization of high-speed digital FIR filters.At the same time,for the problem that the coefficients no longer meet the symmetry after the multiphase decomposition of the FIR filter,the symmetry coefficient factor is constructed.In the FPGA implementation,the use of multipliers can be reduced by half,and the occupation of FPGA resources could be optimized effectively.
作者
赵飞
杨建
ZHAO Fei;YANG Jian(Southwest China Research Institute of Electronic Equipment,Chengdu 610036,China)
出处
《电子信息对抗技术》
北大核心
2022年第5期105-109,共5页
Electronic Information Warfare Technology
