摘要
随着集成电路产业的飞速发展,电子行业对于模拟集成电路的性能提出了更高的要求,如何设计出更高性能的带隙基准引发了许多学者的思考。在这样的背景下,针对高电源电压抑制比(Power supply voltage rejection ratio,PSRR)带隙基准展开了研究,通过选用共源共栅结构运放和在带隙基准电压源主体电路的输出端添加RC低通滤波器两种设计优化策略来改善电路的PSRR性能。基于SMIC 0.13μm CMOS工艺,使用Cadence软件进行电路设计与版图验证。仿真结果表明,温度-40℃~85℃,输出带隙基准电流为5.017μA,输出带隙基准电压为1.21 V,电路的温度系数为6.437 ppm/℃,电源电压抑制比为-90.62 dB,版图面积为8770.06μm~2。版图通过了DRC与LVS验证,电路后仿真得到的性能与前仿真结果差异不大,可以满足性能要求。
With the rapid development of integrated circuit industry,the industry has put forward higher requirements for the performance of analog circuits.How to design a higher performanc bandgap reference has aroused many scholars’thinking.High Power supply voltage rejection ratio(PSRR)bandgap voltage reference was studied.The optimized strategies of adopting cascode operational amplifier and adding RC low-pass filter were used to improve the performance of PSRR.Based on SMIC 0.13μm CMOS process,the circuit was designed and verified by Cadence software.The simulation results show that:in the temperature range of-40℃~85℃,the output bandgap current is 5.017μA,the output bandgap voltage is 1.21 V,the temperature coefficient is 6.437 ppm/℃,the power supply voltage rejection ratio is-90.62 dB at low frequency,and the area is 8770.06μm~2.The layout was verified by DRC and LVS,and the post-simulation was carried out.The performances of the post-simulation are similar to that of the pre-simulation,and still meet the performance requirements.
作者
崔佳旭
李志远
孙艳梅
CUI Jiaxu;LI Zhiyuan;SUN Yanmei(College of Electronic Engineering,Heilongjiang University,Harbin 150080,China)
出处
《黑龙江大学自然科学学报》
CAS
2022年第5期597-603,共7页
Journal of Natural Science of Heilongjiang University
基金
黑龙江省自然科学基金资助项目(LH2019F029)。
关键词
带隙基准
高电源电压抑制比
低温度系数
共源共栅运放
bandgap reference
high power supply rejection ratio
low temperature coefficient
cascode opamp
