摘要
随着电子封装技术的发展,以晶圆级封装为代表的先进封装技术对集成密度、封装尺寸,及其制造和服役可靠性提出了更高的要求.TSV晶圆封装结构具有典型的结构多尺度特征,这对有限元模型的建立带来很大挑战.为此,本文提出了一种层级多尺度方法,并验证了所提方法的有效性.围绕上述研究内容,首先,阐明了层级多尺度方法的原理和计算流程;其次采用层级多尺度方法建立了不同TSV晶圆封装工艺下的有限元模型,模拟研究了TSV转接板工艺制程中晶圆的翘曲演化,并与实验结果相对比;最后,研究了分区数量对层级多尺度方法精度的影响.研究结果表明,计算规模相当情况下,随着分区数量的增加,计算误差明显降低.与实验结果的对比表明,该方法有相对较高的晶圆翘曲预测精度.此外,本文发展的层级多尺度方法具有一定的可移植性,可以应用到其它同类具有多尺度特征的封装结构可靠性分析中,为解决大规模晶圆级封装翘曲预测问题提供了一种新的解决思略.
With the development of electronic packaging technology,wafer-level packaging is one of the representative advanced packaging methods which puts higher requirements on the integration density of the package,package size,and reliability.However,during the packaging processes,excessive wafer warpage is one of the crucial challenges to affect packaging reliability.The TSV wafer packaging structure presents typical multiscale characteristics,which poses a great challenge on the establishment of finite element models.To this end,a hierarchical multiscale approach is proposed in this paper and the effectiveness of the proposed method is verified.First,the rationale and computational process of the hierarchical multiscale approach is elucidated.Finite element model was established using the hierarchical multiscale method to simulate the warpage evolution during the TSV interposer manufacturing processes,and the simulation results agreed quite closely to the experimental results.Finally,the effect of the hierarchical multiscale approach on the accuracy of the model was investigated.The results of the study show that the computational error decreases significantly with the increase of the number of partitions for a comparable computational size.Compared with the experimental results,it shows that the method can effectively improve the predicting accuracy on wafer warpage.In addition,the developed hierarchical multiscale method is portable and can be applied to other packaging structure featuring with multiscale characteristics,providing a solution to the problem of large-scale electronic packaging.
作者
孙国立
秦飞
代岩伟
李宝霞
SUN Guoli;QIN Fei;DAI Yanwei;LI Baoxia(Faculty of Materials and Manufacturing,Beijing University of Technology,Beijing 100124,China;Xi’an Microelectronics Technology Institute,Xi’an 710054,China)
出处
《微电子学与计算机》
2023年第1期130-137,共8页
Microelectronics & Computer
基金
国家自然科学基金(12272012)
西安微电子技术研究所创新基金资助项目(771CX2020001)。
关键词
TSV晶圆
封装
层级多尺度方法
翘曲
有限元模型
TSV wafer
Electronic packaging
Hierarchical multiscale method
Warpage
Finite element model
