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基于GND采样技术的逐次逼近型模数转换器设计 被引量:1

Design of Successive Approximation ADC Based on Ground Sampling Technique
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摘要 针对柔性压阻式压力传感器输出信号数字化对功耗和面积的要求,设计了一款低功耗逐次逼近型(SAR)模数转换器(ADC).电路采用了基于GND采样的单调开关切换方案降低DAC开关能耗,并使用了分段电容阵列,在进一步降低切换功耗的同时,还缩减了整体电路的面积开销.此外,电路还设计了两级预放大器来降低动态比较器的噪声和失调,采用动态元件匹配技术(DEM)来提高ADC的线性度.在0.18μm 1P6M CMOS工艺下实现了该ADC的电路设计和版图绘制,芯片内核面积约630μm×575μm,在1.8 V的电源电压下功耗为25.7μW.流片测试结果显示:SAR ADC在250 kHz的采样率下以11 bit输出时,信噪失真比SNDR为65.0 dB,有效位数ENOB为10.51 bit. To meet the requirements of power consumption and area for the output signal quantization of the flexible piezoresistive sensor, this paper presents a low-power successive approximation(SAR) analog-to-digital converter(ADC). The monotonic switching method based on the ground sampling technique minimizes DAC switching energy, while a split-capacitor DAC achieves low power in an area efficient manner. In addition,a comparator using a two-stage dynamic preamplifier was proposed to diminish the offset and noise. And dynamic element matching(DEM) techniques are employed to enhance linearity. Circuit design and layout drawing of the proposed SAR ADC were realized in 0.18 μm 1P6M CMOS technology,which occupies an active area of 630 μm×575 μm. The SAR ADC consumes 25.7 μW at 1.8 V supply voltage.The measurement results at a sampling rate of 250 kHz show that this 11-bit ADC achieves a signal-to-noise-and-distortion ratio(SNDR) of 65.0 dB and an efficient number of bits(ENOB) of 10.51 bit.
作者 叶茂 楚银英 赵毅强 YE Mao;CHU Yinying;ZHAO Yiqiang(School of Microelectronics,Tianjin University,Tianjin 300072,China;Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology,Tianjin University,Tianjin 300072,China)
出处 《湖南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2023年第2期129-137,共9页 Journal of Hunan University:Natural Sciences
基金 国家重点研发计划资助项目(2018YFB1304700)。
关键词 逐次逼近型模数转换器 GND采样 动态元件匹配 successive approximation(SAR)analog-to-digital converter(ADC) ground sampling dynamic element matching(DEM)
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