摘要
针对传统UART IP核设计中存在的使用场景单一、不能支持同步通信的不足,设计了一款基于APB总线接口的USART外设。采用模块化设计方式通过Verilog语言对APB总线数据传输模块、寄存器组模块、串行数据发送模块、串行数据接收模块、波特率发生模块进行了详细设计,并使用Simvision软件通过UVM验证方法学对电路的异步/同步通信功能进行验证。验证结果表明,设计的IP核在实现异步数据收发的基础上可实现基于SPI协议的同步数据收发,相较于传统的UART IP核设计,具有更强的普适性。
This article proposes a USART peripheral based on APB bus interface to address the shortcomings of single usage scenarios and inability to support synchronous communication in traditional UART IP core design.The APB bus data transmission module,register group module,serial data sending module,serial data receiving module,and baud rate generation module are designed in detail using a modular design approach and Verilog language.The asynchronous/synchronous communication function of the circuit is verified using Simvision software and UVM verification methodology.The verification results indicate that the designed IP core can also achieve synchronous data transmission based on SPI protocol on the basis of asynchronous data transmission,and has stronger universality compared to traditional UART IP core design.
作者
朱亚琦
侯晓娟
Zhu Yaqi;Hou Xiaojuan(Key Laboratory of Instrumentation Science and Dynamic Measurement,Ministry of Education,North University of China,Taiyuan 030051,China)
出处
《单片机与嵌入式系统应用》
2023年第8期15-19,23,共6页
Microcontrollers & Embedded Systems
基金
山西省应用基础研究计划资助项目(20210302123059)
山西省高等学校科技创新项目资助(2020L0326)。
