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基于LVDS的高速远距离传输优化设计 被引量:1

Optimised Design for High-speed Long-distance Transmission Based on LVDS
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摘要 针对远距离高速LVDS信号在传输时存在抗干扰能力差、失锁、误码以及丢数等问题,在硬件和软件两方面都做出相应优化设计。在硬件设计上,发送端采用驱动器实现预加重技术,增大电压输出摆幅,增加磁隔离器,增强抗干扰能力,接收端使用均衡器补偿信号在传输中的损耗;在软件逻辑上,设计了一种新型具有自纠错的6B/10B编码方式,对有效数据增加监督码元,不仅可以均衡频谱来减少串扰,且保障了数据的正确性,满足高速传输的可靠需求。多次试验结果表明,该设计可以实现在100 m双绞线屏蔽电缆下400 Mb/s的无误码可靠传输。 Aiming at the problems of poor interference immunity,loss of locking,mis-coding and loss of numbers in the transmission of long distance high speed LVDS signals,both hardware and software have been optimised.The hardware design uses drivers to implement pre-emphasis technology,increase the voltage output swing and add magnetic isolators to enhance the anti-interference capability,while the receiver uses an equaliser to compensate for signal loss in transmission.The new 6B/10B coding method with self-correction is de-signed to add supervisory code elements to the valid data,not only to balance the spectrum to reduce crosstalk,but also to guarantee the correctness of the data and meet the reliable demand of high-speed transmission.After several tests,it is finally shown that the design can achieve reliable transmission without error codes at 400 Mb/s under 100 m twisted pair shielded cable.
作者 郭红伟 文丰 李辉景 杨志文 Guo Hongwei;Wen Feng;Li Huijing;Yang Zhiwen(Key Laboratory of Instrumentation Science and Dynamic Measurement of Ministry of Education,Science and Technology on Electronic Test and Measurement Laboratory,North University of China,Taiyuan 030051,China)
出处 《单片机与嵌入式系统应用》 2023年第11期41-44,53,共5页 Microcontrollers & Embedded Systems
关键词 低压差分信号 FPGA 6B/10B编码 LVDS FPGA 6B/10B code
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