摘要
在RFID技术不断发展和应用领域不断扩大的背景下,低成本、低功耗是标签芯片设计的重中之重。本文设计了一款数字基带,符合国家标准GB/T 29768的要求,具有低功耗、面积小的特点。该设计采用多时钟域设计、操作数隔离、电路复用等低功耗技术。并且使用Modelsim进行功能验证,验证结果符合预期。采用GSMC 0.13μm工艺,经过逻辑综合和功耗分析,数字基带功耗为2.63μW,布局布线后面积为0.045mm2,满足设计需求。
In the context of the continuous development of RFID technology and the continuous expansion of application fields,low cost and low power consumption are the top priorities of tag chip design.This paper designs a digital baseband,which meets the requirements of the national standard"GB/T 29768",and has the characteristics of low power consumption and small area.The design uses low-power technologies such as multi-clock design,operand isolation,and circuit multiplexing.And using Modelsim for functional verification,the verification results are as expected.Using GMSC 0.13μm process,after logic synthesis and power consumption analysis,the total power consumption of the digital baseband is 2.63μWand the area is 0.045mm2,which meets the design requirements.
作者
曾高峰
李建成
ZENG Gao-feng;LI Jian-cheng(School of Physics and Optoelectronic Engineering)
出处
《中国集成电路》
2023年第11期47-51,共5页
China lntegrated Circuit
