摘要
为了在400 Gb/s以太网物理编码子层(PCS)中实现高速纠错编码,设计了一种递推里德-所罗门(RS)编码电路。该电路通过组合递推因子、输入数据和寄存器数据,可以得到递推RS编码电路的结果。采用VCS+Verdi软件对传统RS编码电路、递推RS编码电路进行仿真,并使用Nangate 45 nm开源工艺进行综合测试。仿真与测试结果表明:相较于并行RS(544,514)编码电路,使用递推RS编码电路可以大幅度减少时间开销;32路递推RS(544,514)编码电路的面积降低了68%,功耗降低了60%。
In order to implement high speed error correction coding in 400 Gb/s Ethernet physical coding sublayer(PCS),a recursive Reed-Solomon(RS)coding circuit is designed.By combining recurrence factor,input data and register data,the result of recursive RS coding circuit can be obtained.VCS+Verdi software is used to simulate the traditional RS coding circuit and the recursive RS coding circuit,and the Nangate 45 nm open source process is used for comprehensive testing.The simulation and test results show that compared with the parallel RS(544,514)coding circuit,the recursive RS coding circuit can greatly reduce the time cost.The area of the 32-channel recurrent RS(544,514)coding circuit is reduced by 68% and the power consumption is reduced by 60%.
作者
韦春雷
吴新春
黄孝兵
WEI Chunlei;WU Xinchun;HUANG Xiaobing(School of Information Science and Technology,Southwest Jiaotong University,Chengdu 611756,China;Qianghua Times(Chengdu)Technology Co.,Ltd.,Chengdu 610041,China)
出处
《光通信技术》
北大核心
2024年第1期71-73,共3页
Optical Communication Technology
基金
四川省科技计划项目(项目编号:2023YFG0137)资助。
