摘要
基于X87指令集架构,在TSMC 65nm的工艺库下,采用SRT-16算法设计一种浮点除法运算单元。SRT-16算法主要是通过采用重叠商与余数计算部分的结构来进行优化处理,使得在原有传统算法SRT-4的基础上增加的电路面积较少,并且使得循环次数减少一半,并且在处理商的结果中引入商的飞速转换技术。通过对基于SystemVerilog自动对比平台的搭建,通过C对比模型,完成自动对比,加速验证的速度,进行功能覆盖统计,完成覆盖率100%。通过DC综合检测电路的时序情况,对电路进行时序优化,完成满足时序要求1.08ns,工作频率为900MHz。
Based on the X87 instruction set architecture and TSMC 65nm process library,this paper uses SRT-16 algorithm to design the floating-point division unit.SRT-16 algorithm is mainly optimized by using the structure of overlapping quotient and remainder calculation part,so that the circuit area increased on the basis of the original traditional algorithm SRT-4 is less,and the number of cycles is doubled.The fly conversion method of quotient is introduced into the result of processing quotient.Through the construction of the automatic comparison platform based on SystemVerilog and the C comparison model,the automatic comparison is completed,the verification speed is accelerated,the function coverage statistics are carried out,and the coverage rate is 100%.The timing of the circuit is comprehensively detected by DC,and the timing of the circuit is optimized.It meets the timing requirements of 1.08 ns and the working frequency is 900 MHz.
作者
赵鹏
ZHAO Peng(School of Information Engineering,Yulin University,Yulin 719000,China)
出处
《微型电脑应用》
2024年第1期65-68,共4页
Microcomputer Applications
基金
陕西省教育厅科学研究计划项目(21JK1006)。
