摘要
在片上系统SoC开发过程中,如何高效准确地进行功能验证与性能分析,是亟待解决的难题。针对目前在FPGA原型平台上对片上网络协议监测手段有限的问题,提出了一种软硬件混合的高效CHI协议监测和分析方法,通过SystemVerilog的直接编程接口DPI连接C代码,由可综合的硬件部分提供共享函数体,不可综合的软件部分通过共享函数体从片上网络协议的各个通道捕捉待测SoC中的CHI报文,进行离线保存或在线检查。实验结果表明,该方法具有硬件资源占用少、可重用性高的优点,离线模式对仿真速率影响不大,在线模式可以在待测SoC运行的同时发现问题,能够实现在原型平台上对CHI协议报文的高效监测,有效加速SoC问题的定位和性能分析。
In the development process of SoC,how to efficiently and accurately perform functional verification and performance analysis is an urgent problem to be solved.Aiming at the current limited monitoring means of Network-on-Chip protocols on FPGA prototype platforms,this paper proposes an efficient monitoring and analysis method with hardware-software mixture for CHI protocols.By connecting C code through the DPI of SystemVerilog,the synthesizable hardware part provides a shared function body,while the non-synthesizable software part captures CHI messages in the SoC under test from various channels of the Network-on-Chip protocol through the shared function body for offline storage or online inspection.Experimental results show that this method has the advantages of low hardware resource occupation and high reusability.The offline mode has little impact on simulation speed,while the online mode can detect problems while the SoC under test is running,enabling efficient monitoring of CHI protocol mes-sages on the prototype platform and effectively accelerating the localization and performance analysis of SoC problems.
作者
赵祉乔
周理
荀长庆
潘国腾
铁俊波
王伟征
ZHAO Zhi-qiao;ZHOU Li;XUN Chang-qing;PAN Guo-teng;TIE Jun-bo;WANG Wei-zheng(School of Computer and Communication Engineering,Changsha University of Science&Technology,Changsha 410114;College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)
出处
《计算机工程与科学》
CSCD
北大核心
2024年第2期224-231,共8页
Computer Engineering & Science
关键词
CHI协议
FPGA
芯片验证
软硬件混合
coherent hub interface(CHI)protocol
FPGA
verification of chip
hardware-software mixture
