摘要
随着集成密度和单片处理速度的不断提升,芯粒集成系统封装(Chiplet SiP)中互连网络日趋复杂且信号与电源完整性、传输能耗问题日趋严重,芯粒与SiP外部的数据交换I/O(Input/Output)容量的提升遭遇瓶颈。为提升芯粒集成度、提高数据传输速率与准确率、降低系统功耗,根据芯粒间通信的最新标准通用芯粒互连技术(Universal chiplet interconnect express, UCIe),利用高速串行计算机扩展总线标准(Peripheral component interconnect express, PCIe)在高速数据存储及传输方面的技术优势,设计出一种芯粒高速I/O通信的架构,并用FPGA验证了此架构的可行性,为UCIe标准的落地提供了一种实现途径。
With increasing integration density and chip processing speeds,the interconnect net-work among chiplet SiP has become increasingly complex,and the difficulty of wiring has sharply ris-en,resulting in a growing concern over signal and power integrity as well as transmission energy con-sumption.As a consequence,the data exchange I/O(Input/Output)capacity between the outside of the SiP and chiplet is constrained.In order to improve chiplet integration,data transmission rate and accuracy,and reduce system power consumption,a chiplet high-speed I/O communication architec-ture is designed.The architecture is based on the latest standard UCIe(Universal chip interconnect ex-press)for inter chip communication.The design takes advantage of PCIe(Peripheral component inter-connect express)bus in high-speed data storage and transmission,an architecture for implementing high-speed I/O communication between Chips is designed.Its feasibility is verified by using FPGA re-sources,which provide an approach for the physical implementation of the UCIe standard.
作者
张转转
缪旻
朱仕梁
段晓龙
ZHANG Zhuanzhuan;MIAO Min;ZHU Shiliang;Duan Xiaolong(Key Laboratory of Information and Communication Systems,Ministry of Information Industry,Beijing Information Science and Technology University,Beijing,100101,CHN;Key Laboratory of the Ministry of Education for Optoelectronic Measurement Technology and Instrument,Beijing Information Science and Technology University,Beijing,100192,CHN;Academy of Smart IC and Network(ASICNet),Beijing Information Science and Technology University,Beijing,100101,CHN)
出处
《固体电子学研究与进展》
CAS
2024年第1期45-49,58,共6页
Research & Progress of SSE
基金
国家自然科学基金资助项目(62074017)。
