摘要
为解决信息处理微系统中双倍速率同步动态随机存储器(Double Data Rate,DDR)复杂互连故障的检出效率和测试成本问题,通过分析DDR典型互连故障模式,将单个存储器件的自动测试设备(Auto Test Equipment,ATE)测试算法与板级系统的系统级测试(System Level Test,SLT)模式相结合,提出面向DDR类存储器的测试算法和实现技术途径。并基于现场可编程门阵列(Field Programmable Gate Array,FPGA)器件实现微系统内DDR互连故障的自测试,完成了典型算法的仿真模拟和实物测试验证。相较于使用ATE测试机台的存储器测试或通过用户层测试软件的测试方案,本文所采用的FPGA嵌入特定自测试算法方案可以实现典型DDR互连故障的高效覆盖,测试效率和测试成本均得到明显改善。
In order to solve the problem of balancing test efficiency and test cost of various complex interconnect faults of Double Data Rate(DDR)devices in information processing microsystems,this paper aims at DDR typical interconnect fault modes and combines the Auto Test Equipment(ATE)test algorithm of a single memory device with the System Level Test(SLT)program of a board-level system.Based on the Field Programmable Gate Array(FPGA)device that comes with the system,the self-test of the DDR interconnection fault in the microsystem is realized,and the simulation verification of the typical algorithm is completed.Compared with single-chip testing using ATE testing machine or running test software through CPU,the FPGA embedding specific sub-test algorithm scheme adopted in this paper can achieve high coverage of typical DDR interconnection faults,test efficiency and the balance of test costs has been significantly improved.
作者
徐润智
杨宇军
赵超
XU Runzhi;YANG Yujun;ZHAO Chao(Xi'an Microelectronics Technology Institute,Xi'an 710054,China)
出处
《微电子学与计算机》
2024年第3期98-104,共7页
Microelectronics & Computer
