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基于国产FPGA的多源视频信号拼接系统设计

Design of multi-source video signal splicing system based on domestic FPGA
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摘要 针对目前视频拼接技术存在动态视频数据速度慢、分辨率较低的问题,设计了一种能够将两路摄像头和两路高清晰度多媒体接口(high definition multimedia interface,HDMI)输入的动态视频数据进行拼接处理的系统。系统以紫光同创公司Pango logos系列现场可编程门阵列(field programmable gate array,FPGA)器件为核心,由时钟控制、寄存器配置、数据采集、先进先出(first in first out,FIFO)数据存储控制、第3代双倍速率同步动态随机存储(double-data-rate 3 synchronous dynamic RAM,DDR3 SDRAM)等逻辑功能模块组成。设计实现了DDR3 IP核的读写控制、图像缩放及视频拼接算法,使用Inserter和Debugger对主要功能模块进行了仿真测试,并进行了视频采集实验,结果表明,系统能够完成4路动态视频的拼接显示,分辨率达到1920×1080,刷新速率为60 fps,占用的查找表(look up table,LUT)资源为18%。支持多种动态数据输入方式,具有便携性好、帧率分辨率高、片上资源占用率低等特点,可用于动态视频拼接的应用场景。 Aiming at the problems of slow speed and low resolution of dynamic video data in current video splicing technology,a system that can splice dynamic video data input from two cameras and two high definition multimedia interface(HDMI)is designed.The system is based on the Pango logos series field programmable gate array(FPGA)as the core,which is controlled by clock,register configuration,data acquisition,first in first out(FIFO)data storage control,the third generation of double-data-rate 3 synchronous dynamic RAM(DDR3 SDRAM)and other logical function modules.The read-write control,image scaling algorithm and video splicing algorithm of DDR3 IP core are designed and implemented.The Inserter and Debugger are used to conduct simulation tests on the main function modules,and the video acquisition experiment is carried out on the system.The results show that the system can complete the four-channel dynamic video splicing display.The resolution is 1920×1080,the refresh rate is 60 frames per second,and the look up table(LUT)resource is 18%.The system supports a variety of dynamic data input methods,has the characteristics of good portability,high frame rate resolution,low on-chip resource occupancy,and can be applied to dynamic video Mosaic application scenarios.
作者 冯琳 徐伟 Feng Lin;Xu Wei(Collaborative Innovation Center on Forecast and Evaluation of Meteorological Disasters,Nanjing University of Information Science and Technology,Nanjing 210044,China;Jiangsu Key Laboratory of Meteorological Observation and Information Processing,Nanjing University of Information Science and Technology,Nanjing 210044,China)
出处 《国外电子测量技术》 2024年第5期92-98,共7页 Foreign Electronic Measurement Technology
基金 国家自然科学基金(41605121)项目资助。
关键词 多源输入 视频拼接 FPGA DDR3 multiple source input video stitching FPGA DDR3
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