摘要
针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟研究态密度关键参数对器件性能的影响,以此揭示a-IGZO TFTs中制备工艺对导电沟道修复的物理机理.首先,采用结合强度较高的钼/铜双层结构作为栅/源/漏电极,引入BCE方法制备了底栅顶接触(BottomGate Top-Contact,BG-TC)TFTs.其次,建立了适用于BCE技术的a-IGZO TFTs的HCD-DOS模型.随后,基于TCAD(Technology Computer Aided Design)仿真器对态密度关键参数进行数值研究,结果表明,不同态密度参数对a-IGZO TFTs器件转移特性曲线、电学特性以及沟道内部电子浓度分布的影响有所差异.最后,基于HCD-DOS模型探索SiO_(x)钝化层沉积和N_(2)O等离子体处理对器件内部机理的影响.研究发现,N2O等离子体处理对态密度分布和沟道载流子浓度有显著影响,进而导致阈值电压正向漂移.
A high-concentration doped density of states model(HCD-DOS model)was established for amorphous indium gallium zinc oxide(a-IGZO)thin-film transistors(TFTs)with back-channel etch(BCE)technology.The effect of the key parameters of the density of states on the device performance was also investigated by numerical simulation to reveal the physical mechanism of the preparation process to repair the conductive channel in a-IGZO TFTs.Firstly,the molybdenum/copper bilayer structure with high bonding strength was used as gate/source/drain electrodes,and the bottom-gate topcontact(BG-TC)TFTs was prepared by introducing the BCE method.Secondly,the HCD-DOS model of a-IGZO TFTs suitable for BCE technology was developed.Subsequently,the key parameters of the density of states were investigated numerically based on the TCAD(Technology Computer Aided Design)simulator.The results demonstrated that different density of states parameters had different effects on the transfer characteristic curves,electrical characteristics,and electron concentration distribution inside the channel of the a-IGZO TFTs device.At last,the influence of SiOx passivation-layer deposition and N2O plasma treatment on the internal mechanism of the device was explored based on the HCD-DOS model.It was found that N2O plasma treatment had a significant effect on the density of states distribution and channel carrier concentration,which in turn caused the threshold voltage to drift.
作者
蔡坤林
谢应涛
蹇欢
黄雁琳
翁嘉明
CAI Kun-lin;XIE Ying-tao;JIAN Huan;HUANG Yan-lin;WENG Jia-ming(Department of Electronic Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065,China;Department of Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,China)
出处
《电子学报》
EI
CAS
CSCD
北大核心
2024年第5期1591-1600,共10页
Acta Electronica Sinica
基金
国家自然科学基金(No.61804019)
重庆市教委科学技术研究项目(No.KJZD-K202200607)
重庆市研究生科研创新项目(No.CYS22441)。
关键词
非晶铟镓锌氧化物薄膜晶体管
态密度模型
钝化层沉积
等离子体处理
背沟道刻蚀
amorphous indium gallium zinc oxide thin-film transistors
density of states model
passivation-layer deposition
plasma treatment
back-channel etch
