期刊文献+

用0.35μm CMOS工艺实现存储接口单元中的数模混合DLL 被引量:1

Implementation of mixed DLL in the unit of memory interface with 0.35μm CMOS technology
下载PDF
导出
摘要 论述了一种利用0.35mm、双阱、双层金属、双层多晶硅的CMOS工艺所实现的延迟锁定环(DLL)。该DLL用于RISC处理器中存储接口部件的时钟同步。本文介绍了其应用背景,给出了DLL的系统结构,接着分别介绍了鉴相器、电荷泵以及压控延迟线的电路结构,最后给出相关仿真结果。 A kind of DLL, which is fabricated with 0.35mm, double-well, double-metal, doublepoly-silicon CMOS technology is described in this paper. The DLL is used as clock synchronizerin the memory interface unit. The background, the system structure of the DLL, and the circuits offrequency-detector, charge-pump and VCDL are introduced.The related simulation results are alsogiven.
出处 《半导体技术》 CAS CSCD 北大核心 2003年第4期72-75,共4页 Semiconductor Technology
关键词 CMOS工艺 DLL 延迟锁定环 存储接口 压控延迟线 delay locked loop(DLL) memory interface voltage control delay line(VCDL)
  • 相关文献

参考文献1

  • 1LIU S I,et al.Low-power clock-deskew buffer forhigh-speed digital circuit[].IEEE Journal of Solid State Circuits.1999

同被引文献3

  • 1Garlepp B W,Donnelly K S,Kim J,et al.A Portable Digital DLL for High-speed CMOS Interface Circuits[J].IEEE Journal of Solid-state Circuits,1999,34(5).
  • 2Tanoi S,Tanabe T,Takahashi K.A 250-622 MHz Deskew and Jitter-suppressed Clock Buffer Using Two-loop Architecture[J].IEEE Journal of Solid-state Circuits,1996,31(4).
  • 3Kim S J,Hong S H,Wee J K,et al.A Low-jitter Wide-range Skew-calibrated Dual-loop DLL Using Antifuse Circuitry for High-speed DRAM[J].IEEE Journal of Solid-state Circuits,2002,37(6).

引证文献1

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部