摘要
本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系,并分析了新型超标量RISC结构的实现方案,其中包括具有单个执行部件和多个执行部件的结构.对于现存的RISC处理机,执行部件是单个的而且是已经确定的,如何升级为超标量RISC结构并保持其应用软件二进制全兼容,这是一个难题.本文提出一种效能价格比良好的超标量RISC结构,能保持原有的执行部件结构不变动,且满足软件兼容.
This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed. For the existing traditional RISC processors, the execution parts have been already determined, so how to upgrade those RISCs into superscalar architecture, and meanwhile to keep the full binary compatibility in application software is a challenging and significant problem. In this paper, a new design approach of superscalar RISC architecture with the compatibility of uniprocessor structure is proposed. This design approach makes use of a instruction fetch buffer with the combination of parallel processing of conditional code for branching. This design method is feasible and cost-effective.
出处
《小型微型计算机系统》
CSCD
北大核心
1992年第4期1-7,16,共8页
Journal of Chinese Computer Systems
关键词
RISC
执行部件
结构
设计
Superscalar RISC, multiple instruction issue, uniprocessor
